RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1311
Dec 10, 2015
18.3.20 CAN Receive Rule Entry Register jBL (GAFLMLj) (j = 0 to 15)
Address GAFLML0L: F03A4H, GAFLML0H: F03A5H GAFLML1L: F03B0H, GAFLML1H: F03B1H
GAFLML2L: F03BCH, GAFLML2H: F03BDH GAFLML3L: F03C8H, GAFLML3H: F03C9H
GAFLML4L: F03D4H, GAFLML4H: F03D5H GAFLML5L: F03E0H, GAFLML5H: F03E1H
GAFLML6L: F03ECH, GAFLML6H: F03EDH GAFLML7L: F03F8H, GAFLML7H: F03F9H
GAFLML8L: F0404H, GAFLML8H: F0405H GAFLML9L: F0410H, GAFLML9H: F0411H
GAFLML10L: F041CH, GAFLML10H: F041DH GAFLML11L: F0428H, GAFLML11H: F0429H
GAFLML12L: F0434H, GAFLML12H: F0435H GAFLML13L: F0440H, GAFLML13H: F0441H
GAFLML14L: F044CH, GAFLML14H: F044DH GAFLML15L: F0458H, GAFLML15H: F0459H
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
GAFLIDM[15:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 0 GAFLIDM
[15:0]
ID Mask L 0: The corresponding ID bit is not compared.
1: The corresponding ID bit is compared.
R/W
Modify the GAFLMLj register only when the RPAGE bit in the GRWCR register is set to 0 in global reset mode.
• GAFLIDM[15:0] Bits
These bits are used to mask the corresponding ID bit of the receive rule.
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