RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1314
Dec 10, 2015
18.3.23 CAN Receive Rule Entry Register jCH (GAFLPHj) (j = 0 to 15)
Address GAFLPH0L: F03AAH, GAFLPH0H: F03ABH GAFLPH1L: F03B6H, GAFLPH1H: F03B7H
GAFLPH2L: F03C2H, GAFLPH2H: F03C3H GAFLPH3L: F03CEH, GAFLPH3H: F03CFH
GAFLPH4L: F03DAH, GAFLPH4H: F03DBH GAFLPH5L: F03E6H, GAFLPH5H: F03E7H
GAFLPH6L: F03F2H, GAFLPH6H: F03F3H GAFLPH7L: F03FEH, GAFLPH7H: F03FFH
GAFLPH8L: F040AH, GAFLPH8H: F040BH GAFLPH9L: F0416H, GAFLPH9H: F0417H
GAFLPH10L: F0422H, GAFLPH10H: F0423H GAFLPH11L: F042EH, GAFLPH11H: F042FH
GAFLPH12L: F043AH, GAFLPH12H: F043BH GAFLPH13L: F0446H, GAFLPH13H: F0447H
GAFLPH14L: F0452H, GAFLPH14H: F0453H GAFLPH15L: F045EH, GAFLPH15H: F045FH
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
GAFLDLC[3:0] GAFLPTR[11:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 12 GAFLDLC
[3:0]
Receive Rule DLC
b15 b14 b13 b12
0 0 0 0 : DLC check is disabled.
0 0 0 1 : 1 data byte
0 0 1 0 : 2 data bytes
0 0 1 1 : 3 data bytes
0 1 0 0 : 4 data bytes
0 1 0 1 : 5 data bytes
0 1 1 0 : 6 data bytes
0 1 1 1 : 7 data bytes
1 X X X : 8 data bytes
R/W
11 to 0 GAFLPTR
[11:0]
Receive Rule Label Set the 12-bit label information. R/W
Modify the GAFLPHj register only when the RPAGE bit in the GRWCR register is set to 0 in global reset mode.
• GAFLDLC[3:0] Bits
These bits are used to set the minimum data length necessary for receiving messages. If the data length of a
message that is being filtered is equal to or larger than the value set by the GAFLDLC[3:0] bits, the message
passes the DLC check. Setting these bits to B'0000 disables the DLC check function allowing messages with
any data length to pass the DLC check.
• GAFLPTR [11:0] Bits
These bits are used to set a 12-bit label to be attached to messages that have passed through the filter. A label
is attached when a message is stored in the receive buffer or the FIFO buffer.
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