RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1285
Dec 10, 2015
18.3.1 CANi Bit Configuration Register L (CiCFGL) (i = 0)
Address C0CFGLL: F0300H, C0CFGLH: F0301H
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
— — — — — — BRP[9:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to
10
— Reserved
These bits are always read as 0. The write value should
always be 0.
R
9 to 0 BRP[9:0] Prescaler Division Ratio Set
When these bits are set to P (0 to 1023), the baud rate
prescaler divides f
CAN by P + 1.
R/W
Modify the CiCFGL register only in channel reset mode or channel halt mode. Set this register in channel reset mode
before making a transition to channel communication mode or channel halt mode. For setting bit timing, see 18.10 Initial
Settings.
• BRP[9:0] Bits
The CANi Tq clock (f
CANTQi) is obtained by the CAN clock (fCAN) and setting the clock division ratio with the
BRP[9:0] bits and one clock cycle of the CANi Tq clock is 1 Time Quantum (Tq).
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