RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1327
Dec 10, 2015
18.3.35 CAN Receive FIFO Status Register m (RFSTSm) (m = 0, 1)
Address RFSTS0L: F0340H, RFSTS0H: F0341H
RFSTS1L: F0342H, RFSTS1H: F0343H
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
— — RFMC[5:0] — — — — RFIF RFMLT RFFLL RFEMP
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Bit Symbol Bit Name Description R/W
15, 14 — Reserved These bits are always read as 0. The write value should
always be 0.
R
13 to 8 RFMC[5:0] Receive FIFO Unread
Message Counter
The number of unread messages stored in the receive FIFO
buffer is displayed.
R
7 to 4 — Reserved These bits are always read as 0. The write value should
always be 0.
R
3 RFIF Receive FIFO Interrupt
Request Flag
0: No receive FIFO interrupt request is present.
1: A receive FIFO interrupt request is present.
R/(W)
Note
2 RFMLT Receive FIFO Message Lost
Flag
0: No receive FIFO message is lost.
1: A receive FIFO message is lost.
R/(W)
Note
1 RFFLL Receive FIFO Buffer Full
Status Flag
0: The receive FIFO buffer is not full.
1: The receive FIFO buffer is full.
R
0 RFEMP Receive FIFO Buffer Empty
Status Flag
0: The receive FIFO buffer contains unread messages.
1: The receive FIFO buffer contains no unread message
(buffer empty).
R
Note The only effective value for writing to this flag bit is 0, which clears the bit. Otherwise writing to the bit results in
retention of its state. To write 0 to this flag bit, write by using an 8-bit data transfer instruction or a 16-bit data
transfer instruction.
• RFMC[5:0] Flag
This flag indicates the number of unread messages in the receive FIFO buffer. This flag becomes H'00 when the
RFE bit in the RFCCm register is set to 0.
• RFIF Flag
This flag is set to 1 when the receive FIFO interrupt request generation conditions set by the RFIGCV[2:0] bits
and the RFIM bit in the RFCCm register are met. This flag is cleared to 0 in global reset mode or by writing 0 to
this flag. Modify this bit only in global operating mode or global test mode.
• RFMLT Flag
This flag is set to 1 when it is attempted to store a new message while the receive FIFO buffer is full. In this
case, the new message is discarded.
This flag is cleared to 0 in global reset mode or by writing 0 to this flag.
Modify this bit only in global operating mode or global test mode.
• RFFLL Flag
This flag is set to 1 when the number of messages stored in the receive FIFO buffer matches the FIFO buffer
depth set by the RFDC[2:0] bits in the RFCCm register.
If the number of messages stored in the receive FIFO buffer becomes smaller than the FIFO buffer depth set by
the RFDC[2:0] bits, this flag is cleared to 0. This flag is also cleared to 0 when the RFE bit in the RFCCm
register is set to 0 (no receive FIFO buffer is used) or in global reset mode.
<R>
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