Renesas RL78/F14

RL78/F13, F14 CHAPTER 26 VOLTAGE DETECTOR
R01UH0368EJ0210 Rev.2.10 1571
Dec 10, 2015
26.4.3 When used as interrupt and reset mode
 When starting operation
Specify the operation mode (the interrupt and reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage
(V
LVDH, VLVDL) by using the option byte 000C1H/020C1H.
Start in the following initial setting state.
 Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level
register (LVIS))
 When the option byte LVIMDS1 is set to 1 and LVIMDS0 is clear to 0, the initial value of the LVIS register is set
to 00H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 0 (high-voltage detection level: V
LVDH).
Figures 26-6 shows the Timing of Voltage Detector Reset Signal and Interrupt Signal Generation.
Perform the processing according to Figure 26-7 Processing Procedure After an Interrupt Is Generated and
Figure 26-8 Initial Setting of Interrupt and Reset Mode.