RL78/F13, F14 CHAPTER 12 A/D CONVERTER
R01UH0368EJ0210 Rev.2.10 725
Dec 10, 2015
12.3.8 Conversion result comparison upper limit setting register (ADUL)
This register is used to specify the setting for checking the upper limit of the A/D conversion results.
The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is controlled
in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 12-8).
The ADUL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Figure 12-12. Format of Conversion Result Comparison Upper Limit Setting Register (ADUL)
Address: F0011H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
ADUL ADUL7 ADUL6 ADUL5 ADUL4 ADUL3 ADUL2 ADUL1 ADUL0
Cautions 1. When A/D conversion with 10-bit resolution is selected, the higher eight bits of the 10-bit A/D
conversion result register (ADCR) are compared with the value in the ADUL register.
2. Writing new values to the ADUL and ADLL registers is prohibited while conversion is enabled.
Write new values to these registers while conversion is stopped (ADCE = 0).
3. The setting of the ADUL registers must be greater than that of the ADLL register.
12.3.9 Conversion result comparison lower limit setting register (ADLL)
This register is used to specify the setting for checking the lower limit of the A/D conversion results.
The A/D conversion results and ADLL register value are compared, and interrupt signal (INTAD) generation is controlled
in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 12-8).
The ADLL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 12-13. Format of Conversion Result Comparison Lower Limit Setting Register (ADLL)
Address: F0012H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADLL ADLL7 ADLL6 ADLL5 ADLL4 ADLL3 ADLL2 ADLL1 ADLL0
Cautions 1. When A/D conversion with 10-bit resolution is selected, the higher eight bits of the 10-bit A/D
conversion result register (ADCR) are compared with the value in the ADLL register.
2. Writing new values to the ADUL and ADLL registers is prohibited while conversion is enabled.
Write new values to these registers while conversion is stopped (ADCE = 0).
3. The setting of the ADUL registers must be greater than that of the ADLL register.
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