RL78/F13, F14 CHAPTER 12 A/D CONVERTER
R01UH0368EJ0210 Rev.2.10 716
Dec 10, 2015
12.3.3 A/D converter mode register 1 (ADM1)
This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal.
The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 12-6. Format of A/D Converter Mode Register 1 (ADM1)
Address: FFF32H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADM1 ADTMD1 ADTMD0 ADSCM 0 0 0 ADTRS1 ADTRS0
ADTMD1 ADTMD0 Selection of the A/D conversion trigger mode
0
ï‚´
Software trigger mode
1 0 Hardware trigger no-wait mode
1 1 Hardware trigger wait mode
ADSCM Specification of the A/D conversion mode
0 Sequential conversion mode
1 One-shot conversion mode
ADTRS1 ADTRS0 Selection of the hardware trigger signal
0 0 End of TAU0 channel 1 count or capture interrupt signal (INTTM01)
0 1 Trigger signal generated by the ADTRGS0 and ADTRGS1 registers
Note 1
Event signal selected by ELC
Note 2
1 0 Pretimed signal/alarm interrupt signal (INTRTC)
1 1 Setting prohibited
Notes 1. Only in the RL78/F13.
2. Only in the RL78/F14.
Cautions 1. Only rewrite the value of the ADM1 register while conversion operation is stopped (which is
indicated by the ADCS bit of A/D converter mode register 0 (ADM0) being 0).
2. To complete A/D conversion, specify at least the following time as the hardware trigger
interval:
Hardware trigger no wait mode: 2 f
CLK clocks + A/D conversion time
Hardware trigger wait mode: 2 f
CLK clocks + stabilization wait time + A/D conversion time
3. In modes other than SNOOZE mode, input of the next INTRTC will not be recognized as a
valid hardware trigger for up to four f
CLK cycles after the first INTRTC is input.
Remarks 1.
: don’t care
2. f
CLK: CPU/peripheral hardware clock frequency
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