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Renesas RL78/F14 - Cani Transmit;Receive FIFO Access Register Kch (Cfdf1 K) (I = 0) (K = 0)

Renesas RL78/F14
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RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1350
Dec 10, 2015
18.3.54 CANi Transmit/Receive FIFO Access Register kCH (CFDF1k) (i = 0) (k = 0)
Address CFDF10L: F05EAH, CFDF10H: F05EBH
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
CFDB3[7:0] CFDB2[7:0]
After Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit Symbol Bit Name Description R/W
15 to 8 CFDB3[7:0] Transmit/Receive FIFO Buffer Data
Byte 3
When CFM[1:0] value is B'01 (transmit mode):
Set the transmit/receive FIFO buffer data.
When CFM[1:0] value is B'00 (receive mode):
The message data stored in the transmit/receive
FIFO buffer can be read.
R/W
7 to 0 CFDB2[7:0] Transmit/Receive FIFO Buffer Data
Byte 2
R/W
Modify these bits only when the CFM[1:0] value in the CFCCHk register is B'01.
This register is readable only when the CFM[1:0] value is B'00. When the CFDLC [3:0] value in the CFPTRk register is
smaller than B'1000, data bytes for which no data is set are read as H'00.
This register can be read/written when the RPAGE bit in the GRWCR register is 1.

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