RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1289
Dec 10, 2015
• BOEIE Bit
When the BOEF flag in the CiERFLL register is set to 1 with the BOEIE bit set to 1, an error interrupt request is
generated. Modify this bit only in channel reset mode.
• EPIE Bit
When the EPF flag in the CiERFLL register is set to 1 with the EPIE bit set to 1, an error interrupt request is
generated. Modify this bit only in channel reset mode.
• EWIE Bit
When the EWF flag in the CiERFLL register is set to 1 with the EWIE bit set to 1, an error interrupt request is
generated. Modify this bit only in channel reset mode.
• BEIE Bit
When the BEF flag in the CiERFLL register is set to 1 with the BEIE bit set to 1, an error interrupt request is
generated. Modify this bit only in channel reset mode.
• RTBO Bit
Setting this bit to 1 (forcible return from the bus off state) in the bus off state forcibly returns the state from the
bus off state to the error active state. This bit is automatically cleared to 0. Setting this bit to 1 clears the
TEC[7:0] and REC[7:0] bits in the CiSTSH register to H'00 and also clears the BOSTS flag in the CiSTSL
register to 0 (not in bus off state). The other registers remain unchanged. No bus off recovery interrupt request
due to return from the bus off state is generated. Use this bit only when the BOM[1:0] bits in the CiCTRH
register are B'00 (ISO11898-1 compliant).
A delay of up to 1 CAN bit time occurs after the RTBO bit is set to 1 until the CAN module transitions to the error
active state. Set this bit to 1 in channel communication mode.
• CSLPR Bit
Setting this bit to 1 places the channel in channel stop mode.
Clearing this bit to 0 makes the channel leave from channel stop mode.
Do not modify this bit while the CAN channel is in channel communication mode or channel halt mode.
• CHMDC[1:0] Bits
These bits are used to select a channel mode (channel communication mode, channel reset mode, or channel
halt mode). For details, see 18.4.2 Channel Modes. Setting the CSLPR bit to 1 in channel reset mode allows
transition to channel stop mode. Do not set the CHMDC[1:0] bits to B'11. When the CAN module has
transitioned to channel halt mode depending on the setting of the BOM[1:0] bits, the CHMDC[1:0] bits
automatically becomes B'10.
To Next Page
Loading...
