RL78/F13, F14 CHAPTER 16 SERIAL INTERFACE IICA
R01UH0368EJ0210 Rev.2.10 1033
Dec 10, 2015
Figure 16-9. Format of IICA Control Register 01 (IICCTL01) (2/2)
CLD0 Detection of SCLA0 pin level (valid only when IICE0 = 1)
0 The SCLA0 pin was detected at low level.
1 The SCLA0 pin was detected at high level.
Condition for clearing (CLD0 = 0) Condition for setting (CLD0 = 1)
When the SCLA0 pin is at low level
When IICE0 = 0 (operation stop)
Reset
When the SCLA0 pin is at high level
DAD0 Detection of SDAA0 pin level (valid only when IICE0 = 1)
0 The SDAA0 pin was detected at low level.
1 The SDAA0 pin was detected at high level.
Condition for clearing (DAD0 = 0) Condition for setting (DAD0 = 1)
When the SDAA0 pin is at low level
When IICE0 = 0 (operation stop)
Reset
When the SDAA0 pin is at high level
SMC0 Operation mode switching
0 Operates in standard mode (fastest transfer rate: 100 kbps).
1 Operates in fast mode (fastest transfer rate: 400 kbps) or fast mode plus (fastest transfer rate: 1
Mbps).
DFC0 Digital filter operation control
0 Digital filter off.
1 Digital filter on.
Digital filter can be used only in fast mode.
In fast mode and fast mode plus, the transfer clock does not vary, regardless of the DFC0 bit being set (1) or
cleared (0).
The digital filter is used for noise elimination in fast mode and fast mode plus.
PRS0 Control of the operation clock for IICA (fMCK)
0 Selects fCLK (1 MHz ≤ fCLK ≤ 20 MHz).
1 Selects fCLK/2 (20 MHz < fCLK).
Cautions 1. The fastest operation frequency of the operation clock for IICA (f
MCK) is 20 MHz (max.).
Set bit 0 (PRS0) of the IICA control register 01 (IICCTL01) to 1 only when the fCLK exceeds
20 MHz.
2. Note the minimum f
CLK operation frequency when setting the transfer clock. The
minimum fCLK operation frequency for serial interface IICA is determined according to
the mode.
Fast mode: f
CLK = 3.5 MHz (min.)
Fast mode plus: f
CLK = 10 MHz (min.)
Normal mode: f
CLK = 1 MHz (min.)
Remark IICE0: Bit 7 of IICA control register 00 (IICCTL00)
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