RL78/F13, F14 CHAPTER 16 SERIAL INTERFACE IICA
R01UH0368EJ0210 Rev.2.10 1039
Dec 10, 2015
Cautions 1. The fastest operation frequency of the operation clock for IICA (fMCK) is 20 MHz (max.). Set bit 0
(PRS0) of the IICA control register 01 (IICCTL01) to 1 only when the fCLK exceeds 20 MHz.
2. Note the minimum f
CLK operation frequency when setting the transfer clock. The minimum fCLK
operation frequency for serial interface IICA is determined according to the mode.
Fast mode: f
CLK = 3.5 MHz (min.)
Fast mode plus: f
CLK = 10 MHz (min.)
Normal mode: f
CLK = 1 MHz (min.)
Remarks 1. Calculate the rise time (tR) and fall time (tF) of the SDAA0 and SCLA0 signals separately, because they
differ depending on the pull-up resistance and wire load.
2. IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
t
F: SDAA0 and SCLA0 signal falling times
t
R: SDAA0 and SCLA0 signal rising times
f
MCK: Frequency of the IICA operation clock
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