Renesas RL78/F14

RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1272
Dec 10, 2015
Table 18-3. List of CAN Module Registers (10/22)
Address Special Function Register (SFR) Name Symbol R/W Access Size After
Reset
1 bit 8 bits 16 bits
F042EH CAN receive rule entry register 11CH
Note 1
GAFLPH11L GAFLPH11 R/W — √ √ 0000H
F042FH GAFLPH11H — √
F042EH CAN receive buffer register 8DH
Note 2
RMDF38L RMDF38 R — √ √ 0000H
F042FH RMDF38H — √
F0430H CAN receive rule entry register 12AL
Note 1
GAFLIDL12L GAFLIDL12 R/W — √ √ 0000H
F0431H GAFLIDL12H — √
F0430H CAN receive buffer register 9AL
Note 2
RMIDL9L RMIDL9 R — √ √ 0000H
F0431H RMIDL9H — √
F0432H CAN receive rule entry register 12AH
Note 1
GAFLIDH12L GAFLIDH12 R/W — √ √ 0000H
F0433H GAFLIDH12H — √
F0432H CAN receive buffer register 9AH
Note 2
RMIDH9L RMIDH9 R — √ √ 0000H
F0433H RMIDH9H — √
F0434H CAN receive rule entry register 12BL
Note 1
GAFLML12L GAFLML12 R/W — √ √ 0000H
F0435H GAFLML12H — √
F0434H CAN receive buffer register 9BL
Note 2
RMTS9L RMTS9 R — √ √ 0000H
F0435H RMTS9H — √
F0436H CAN receive rule entry register 12BH
Note 1
GAFLMH12L GAFLMH12 R/W — √ √ 0000H
F0437H GAFLMH12H — √
F0436H CAN receive buffer register 9BH
Note 2
RMPTR9L RMPTR9 R — √ √ 0000H
F0437H RMPTR9H — √
F0438H CAN receive rule entry register 12CL
Note 1
GAFLPL12L GAFLPL12 R/W — √ √ 0000H
F0439H GAFLPL12H — √
F0438H CAN receive buffer register 9CL
Note 2
RMDF09L RMDF09 R — √ √ 0000H
F0439H RMDF09H — √
F043AH CAN receive rule entry register 12CH
Note 1
GAFLPH12L GAFLPH12 R/W — √ √ 0000H
F043BH GAFLPH12H — √
F043AH CAN receive buffer register 9CH
Note 2
RMDF19L RMDF19 R — √ √ 0000H
F043BH RMDF19H — √
F043CH CAN receive rule entry register 13AL
Note 1
GAFLIDL13L GAFLIDL13 R/W — √ √ 0000H
F043DH GAFLIDL13H — √
F043CH CAN receive buffer register 9DL
Note 2
RMDF29L RMDF29 R — √ √ 0000H
F043DH RMDF29H — √
F043EH CAN receive rule entry register 13AH
Note 1
GAFLIDH13L GAFLIDH13 R/W — √ √ 0000H
F043FH GAFLIDH13H — √
F043EH CAN receive buffer register 9DH
Note 2
RMDF39L RMDF39 R — √ √ 0000H
F043FH RMDF39H — √
F0440H CAN receive rule entry register 13BL
Note 1
GAFLML13L GAFLML13 R/W — √ √ 0000H
F0441H GAFLML13H — √
F0440H CAN receive buffer register 10AL
Note 2
RMIDL10L RMIDL10 R — √ √ 0000H
F0441H RMIDL10H — √
F0442H CAN receive rule entry register 13BH
Note 1
GAFLMH13L GAFLMH13 R/W — √ √ 0000H
F0443H GAFLMH13H — √
Notes 1. These registers are allocated to RAM window 0 for the CAN module (receive rules and CAN RAM test
register). When setting these registers, set the RPAGE bit in the GRWCR register to 0.
2. These registers are allocated to RAM window 1 for the CAN module (receive buffer, receive FIFO buffer,
transmit/receive FIFO buffer, transmit buffer, and transmit history data). When setting these registers, set the
RPAGE bit in the GRWCR register to 1.