RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1291
Dec 10, 2015
• BOM[1:0] Bits
These bits are used to select a bus off recovery mode of the CAN module.
When the BOM[1:0] bits are set to B'00, return to the error active state from the bus off state is compliant with
the CAN specifications. That is, the CAN module reenters the CAN communication (error active state) after 11
consecutive recessive bits are detected 128 times. A bus off recovery interrupt request is generated at the time
of return from the bus off state. Even if the CHMDC[1:0] bits are set to B'10 (channel halt mode) before
recessive bits are detected 128 times, the CAN module does not transition to channel halt mode until recessive
bits are detected 128 times.
When the CAN module reaches the bus off state while the BOM[1:0] bits are set to B'01, the CHMDC[1:0] bits in
the CiCTRL register are set to B'10 and the CAN module transitions to channel halt mode. No bus off recovery
interrupt request is generated at the time of return from the bus off state and the TEC[7:0] and REC[7:0] bits in
the CiSTSH register are cleared to H'00.
When the CAN module reaches the bus off state when the BOM[1:0] bits are set to B'10, the CHMDC[1:0] bits
are set to B'10 and the CAN module transitions to channel halt mode after return from the bus off state (11
consecutive recessive bits are detected 128 times). A bus off recovery interrupt request is generated at the time
of return from the bus off state and the TEC[7:0] and REC[7:0] bits are cleared to H'00.
When the BOM[1:0] bits are set to B'11 and the CHMDC[1:0] bits are set to B'10 while the CAN module is in the
bus off state, the CAN module transitions to channel halt mode. No bus off recovery interrupt request is
generated at the time of return from the bus off state and the TEC[7:0] and REC[7:0] bits are cleared to H'00.
However, if 11 consecutive recessive bits are detected 128 times and the CAN module has recovered to the
error active state from the bus off state before the CHMDC[1:0] bits are set to B'10, a bus off recovery interrupt
request is generated.
If the CPU requests transition to channel reset mode at the same time when the CAN module transitions to
channel halt mode (at bus off entry when the BOM[1:0] bits are B'01 or at bus off end when the BOM[1:0] bits
are B'10), the CPU's request takes precedence. Modify these bits only in channel reset mode.
• TAIE Bit
When transmit abort of the transmit buffer is completed with the TAIE bit set to 1, an interrupt request is
generated. Modify this bit only in channel reset mode.
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