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Renesas RL78/F14 User Manual

Renesas RL78/F14
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RL78/F13, F14 CHAPTER 18 CAN INTERFACE (RS-CAN LITE)
R01UH0368EJ0210 Rev.2.10 1358
Dec 10, 2015
• TMTR Bit
Setting this bit to 1 transmits the message stored in the transmit buffer.
The TMTR bit is cleared to 0 when any of the following conditions is met, but is not cleared by writing 0 by the
program.
• Transmission has been completed.
• Transmit abort has been completed by setting the TMTAR bit to 1.
• An error or arbitration lost has been detected with the TMOM bit set to 1.
Set the TMTR bit to 1 when the TMTRF[1:0] value in the TMSTSp register is B'00.

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Renesas RL78/F14 Specifications

General IconGeneral
BrandRenesas
ModelRL78/F14
CategoryComputer Hardware
LanguageEnglish

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