Renesas RL78/F14 User Manual

RL78/F13, F14 CHAPTER 21 INTERRUPT FUNCTIONS
R01UH0368EJ0210 Rev.2.10 1475
Dec 10, 2015
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 55 indicates the lowest priority.
2. Basic configuration types (A) to (F) correspond to (A) to (F) in Figure 21-1.
3. When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
4. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is cleared to 0.
5. Provided only in products of Groups D and E.
6. Provided only in Group E products.
7. To determine whether the actual interrupt source is INTP4 or INTSPM, read the INTFLG00 bit in the
INTFLG0 register or the stack pointer.
8. To determine whether the actual interrupt source is INTP5 or INTCMP0, read the INTFLG01 and
INTFLG06 bits in the INTFLG0 register.
9. To determine whether the actual interrupt source is INTP13 or INTCLM, read the INTFLG07 bit in the
INTFLG0 register and SELPLLS bit in the PLLSTS register.

Renesas RL78/F14 Specifications

General

Brand	Renesas
Model	RL78/F14
Category	Computer Hardware
Language	English