RL78/F13, F14 CHAPTER 24 RESET FUNCTION
R01UH0368EJ0210 Rev.2.10 1547
Dec 10, 2015
Table 24-2. States of Hardware After Acceptance of a Reset (1/4)
Hardware After Acceptance of a Reset
Note 1
Program counter (PC) The contents of the reset vector
table (0000H, 0001H) are set.
Stack pointer (SP) Undefined
Program status word (PSW) 06H
RAM Data memory Undefined
General-purpose registers Undefined
Port mode select register (PMS) 00H
Noise filter enable registers 0 to 2 (NFEN0 to NFEN2) 00H
Peripheral enable registers 0 to 2 (PER0 to PER2) 00H
High-speed on-chip oscillator frequency select register (HOCODIV) Undefined
High-speed on-chip oscillator trimming register (HIOTRM) Note 2
Operation speed mode control register (OSMC) 00H
Port register 0 (P0) 00H
Port register 1 (P1) 00H
Port register 3 (P3) 00H
Port register 4 (P4) 00H
Port register 5 (P5) 00H
Port register 6 (P6) 00H
Port register 7 (P7) 00H
Port register 8 (P8) 00H
Port register 9 (P9) 00H
Port register 10 (P10) 00H
Port register 12 (P12) Undefined
Port register 13 (P13) Undefined
Port register 14 (P14) 00H
Port register 15 (P15) 00H
Serial data register 00 (SDR00) 0000H
Serial data register 01 (SDR01) 0000H
Timer data register 00 (TDR00) 0000H
Timer data register 01 (TDR01/L/H) 00H
10-bit A/D conversion result register (ADCR) 0000H
8-bit A/D conversion result register (ADCRH) 00H
Port mode register 0 (PM0) FFH
Port mode register 1 (PM1) FFH
Port mode register 3 (PM3) FFH
Port mode register 4 (PM4) FFH
Port mode register 5 (PM5) FFH
Port mode register 6 (PM6) FFH
Port mode register 7 (PM7) FFH
Port mode register 8 (PM8) FFH
Port mode register 9 (PM9) FFH
Port mode register 10 (PM10) FFH
Port mode register 12 (PM12) FFH
Port mode register 14 (PM14) FFH
Port mode register 15 (PM15) FFH
A/D converter mode register 0 (ADM0) 00H
Analog input channel specification register (ADS) 00H
A/D converter mode register 1 (ADM1) 00H
D/A conversion value setting register 0 (DACS0) 00H
D/A converter mode register (DAM) 00H
Key return mode register (KRM) 00H
External interrupt rising edge enable register 0 (EGP0) 00H
(Notes and Remark are given below Table 24-2, States of Hardware After Acceptance of a Reset (4/4).)