Renesas RL78/F14 - Page 415

RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 383
Dec 10, 2015
Figure 5-12. Format of Peripheral Enable Register 1 (PER1) (2/2)
Address: F02C0H After reset: 00H R/W
Symbol <7> 6 <5> <4> <3> 2 1 <0>
PER1 DACEN 0 CMPEN
TRD0EN DTCEN 0 0 TRJ0EN
DTCEN Control of DTC input clock supply
0
Stops input clock supply.
 DTC cannot run.
1
Enables input clock supply.
 DTC can run.
TRJ0EN Control of timer RJ0 input clock supply
0
Stops input clock supply.
 SFR used by timer RJ0 cannot be written.
 Timer RJ0 is in the reset status.
1
Enables input clock supply.
 SFR used by timer RJ0 can be read and written.