Renesas RL78/F14 User Manual

RL78/F13, F14 CHAPTER 5 CLOCK GENERATOR
R01UH0368EJ0210 Rev.2.10 419
Dec 10, 2015
Table 5-3. Changing CPU Clock (7/7)
CPU Clock Conditions before Change Processing after Change
Before Change After Change
PLL clock
High-speed on-chip
oscillator clock
The high-speed on-chip oscillator starts
oscillation, and the high-speed on-chip
oscillator clock is selected as the main system
clock.
 HIOSTOP = 0, MCS = 0
The PLL clock can be stopped.
(PLLON = 0)
X1 clock
X1 oscillation is stable, and the high-speed
system clock is selected as the main system
clock.
 OSCSEL = 1, EXCLK = 0, MSTOP = 0
 After elapse of oscillation stabilization time
 MCS = 1
External main system
clock
External clock input from the EXCLK pin is
enabled, and the high-speed system clock is
selected as the main system clock.
 OSCSEL = 1, EXCLK = 1, MSTOP = 0
 SELLOSC = 0, MCS = 1
Remark For details about the register flag settings for stopping the target clock during the processing after change and
conditions before the clock is stopped, see 5.6.9 Conditions Before Clock Oscillation Is Stopped.

Renesas RL78/F14 Specifications

General

Brand	Renesas
Model	RL78/F14
Category	Computer Hardware
Language	English