RL78/F13, F14 CHAPTER 6 TIMER ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 484
Dec 10, 2015
(3) Operation of TOmn pin in slave channel output mode (TOMmn = 1)
(a) When timer output level register m (TOLm) setting has been changed during timer operation
When the TOLm register setting has been changed during timer operation, the setting becomes valid at the
generation timing of the TOmn pin change condition. Rewriting the TOLm register does not change the output
level of the TOmn pin.
The operation when TOMmn is set to 1 and the value of the TOLm register is changed while the timer is operating
(TEmn = 1) is shown below.
Figure 6-38. Operation when TOLm Register Has Been Changed during Timer Operation
Remarks 1. Set: The output signal of the TOmn pin changes from inactive level to active level.
Reset: The output signal of the TOmn pin changes from active level to inactive level.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7)
3. Unit 1 is not provided in the Group A products.
Channels 7 to 4 of unit 1 are not provided in the Group B, C, and D products.
(b) Set/reset timing
To realize 0%/100% output at PWM output, the TOmn pin/TOmn bit set timing at master channel timer interrupt
(INTTMmn) generation is delayed by 1 count clock by the slave channel.
If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Figure 6-39 shows the set/reset operating statuses where the master/slave channels are set as follows.
Master channel: TOEmn = 1, TOMmn = 0, TOLmn = 0
Slave channel: TOEmp = 1, TOMmp = 1, TOLmp = 0
Set
Reset
Set
Reset
Set
TOmn
(output)
Reset
Set
Reset
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