RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 584
Dec 10, 2015
Figure 8-15. Format of Timer RD Digital Filter Function Select Register i (TRDDFi) (i = 0 or 1)
[PWM Function, Reset Synchronous PWM Mode, Complementary PWM Mode, and PWM3 Mode]
Address: F026AH (TRDDF0), F026BH (TRDDF1) After Reset: 00H
Note
Symbol 7 6 5 4 3 2 1 0
TRDDFi DFCK1 DFCK0 PENB1 PENB0 DFD DFC DFB DFA
DFCK1 DFCK0 TRDIOAi pin pulse forced cutoff control R/W
0 0 Forced cutoff disabled R/W
0 1 High-impedance output
1 0 Low output
1 1 High output
Set these bits to 00B (forced cutoff disabled) if the corresponding pin is not used as a timer RD output port in
these modes. Also, set these bits while the count is stopped.
PENB1 PENB0 TRDIOBi pin pulse forced cutoff control R/W
0 0 Forced cutoff disabled R/W
0 1 High-impedance output
1 0 Low output
1 1 High output
Set these bits to 00B (forced cutoff disabled) if the corresponding pin is not used as a timer RD output port in
these modes. Also, set these bits while the count is stopped.
DFD DFC TRDIOCi pin pulse forced cutoff control R/W
0 0 Forced cutoff disabled R/W
0 1 High-impedance output
1 0 Low output
1 1 High output
Set these bits to 00B (forced cutoff disabled) if the corresponding pin is not used as a timer RD output port in
these modes. Also, set these bits while the count is stopped.
DFB DFA TRDIODi pin pulse forced cutoff control R/W
0 0 Forced cutoff disabled R/W
0 1 High-impedance output
1 0 Low output
1 1 High output
Set these bits to 00B (forced cutoff disabled) if the corresponding pin is not used as a timer RD output port in
these modes. Also, set these bits while the count is stopped.
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and TRD0EN
= 0 in the PER1 register. If it is necessary to read the initial value, set f
CLK to fIH and TRD0EN = 1 before reading.
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