RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 589
Dec 10, 2015
Figure 8-20. Format of Timer RD Control Register 0 (TRDCR0) [PWM3 Mode]
Address: F0270H (TRDCR0) After Reset: 00H
Note 1
Symbol 7 6 5 4 3 2 1 0
TRDCR0 CCLR2
CCLR1 CCLR0 CKEG1 CKEG0
TCK2 TCK1 TCK0
CCLR2 CCLR1 CCLR0 TRD0 counter clear select R/W
Set to 001B (TRD0 register is cleared at compare match with TRDGRA0 register). R/W
CKEG1 CKEG0 External clock edge select R/W
Disabled in PWM3 mode. R/W
TCK2 TCK1 TCK0 Count source select R/W
0 0 0
f
CLK, fIH, fPLL, fSUB, fIL
Note 2
R/W
0 0 1 fCLK/2
0 1 0 fCLK/4
0 1 1 fCLK/8
1 0 0 fCLK/32
1 0 1 Do not set.
1 1 0 Do not set.
1 1 1 Do not set.
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and TRD0EN
= 1 before reading.
2. f
CLK is selected when FRQSEL4 = 0 in the user option byte (000C2H/020C2H), (PLLDIV1 = 0 or
SELPLLS = 0), and TRD_CKSEL = 0. fIH is selected when FRQSEL4 = 1 and TRD_CKSEL = 0. fPLL is
selected when (PLLDIV1 = 1 and SELPLLS = 1) and TRD_CKSEL = 0. fSUB is selected when SELLOSC
= 0 and TRD_CKSEL = 1. f
IL is selected when SELLOSC = 1 and TRD_CKSEL = 1. For details, see
Figure 8-40.
When selecting the count source for the timer RD, set the same clock source as the count source for
f
CLK before setting bit 4 (TRD0EN) in the peripheral enable register 1 (PER1).
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