RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 595
Dec 10, 2015
Notes 1. The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and
TRD0EN = 0 in the PER1 register. If it is necessary to read the initial value, set fCLK to fIH and
TRD0EN = 1 before reading.
2. Nothing is assigned to bit 5 in the TRDSR0 register. The write value must be 0 for bit 5. The read value
is 0.
3. When the counter value of timer RDi changes from FFFFH to 0000H, the overflow flag is set to 1. Also,
if the counter value of timer RDi changes from FFFFH to 0000H due to an input capture/compare match
during operation according to the settings of bits CCLR0 to CCLR2 in the TRDCRi register, the overflow
flag is set to 1.
4. The writing results are as follows:
ï‚· Writing 1 has no effect.
ï‚· If the read value is 0, the bit remains unchanged even if 0 is written to it. (Even if the bit is changed
from 0 to 1 after reading and then 0 is written to it, it remains 1.)
ï‚· If the read value is 1, writing 0 to the bit sets it to 0.
Use either (a) or (b) described below to clear each bit of the TRDSRi register.
(a) Set the TRDIERi register to 00H (disabling all interrupts) and then write 0 to all of the status flags.
(b) When at least one bit in the TRDIERi register has the setting 1 and the status flag of an interrupt
source enabled by the corresponding bit is 1, write 0 to all of the status flag bits whose settings
are 1 in the TRDSRi register.
5. Edge selected by bits IOk1 and IOk0 (k = C or D) in the TRDIORCi register.
Including when the TRDBFki bit in the TRDMR register is 1 (TRDGRki is buffer register).
6. Edge selected by bits IOj1 and IOj0 (j = A or B) in the TRDIORAi register.
7. When the DTC is used, bits IMFA, IMFB, IMFC, and IMFD are set to 1 after DTC transfer is completed.
To Next Page
Loading...
Need help?
General
