RL78/F13, F14 CHAPTER 8 TIMER RD
R01UH0368EJ0210 Rev.2.10 606
Dec 10, 2015
Figure 8-36. Format of Timer RD General Registers Ai, Bi, Ci, and Di (TRDGRAi, TRDGRBi,TRDGRCi, TRDGRDi)
(i = 0 or 1) [Reset Synchronous PWM Mode]
Address: F0278H (TRDGRA0), F027AH (TRDGRB0), After Reset: FFFFH
Note
FFF58H (TRDGRC0), FFF5AH (TRDGRD0),
F0288H (TRDGRA1), F028AH (TRDGRB1),
FFF5CH (TRDGRC1), FFF5EH (TRDGRD1)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TRDGRAi — — — — — — — — — — — — — — — —
TRDGRBi
TRDGRCi
TRDGRDi
— Function R/W
Bits 15 to 0 See Table 8-6 TRDGRji Register Functions in Reset Synchronous PWM Mode. R/W
Note The value after reset is undefined when FRQSEL4 = 1 in the user option byte (000C2H/020C2H) and TRD0EN =
0 in the PER1 register. If it is necessary to read the initial value, set f
CLK to fIH and TRD0EN = 1 before reading.
Table 8-6. TRDGRji Register Functions in Reset Synchronous PWM Mode
Register Setting Register Function PWM Output Pin
TRDGRA0 — General register. Set the PWM period. (TRDIOC0, output
inverted every
PWM period)
TRDGRB0 — General register. Set the changing point of PWM1 output. TRDIOB0
TRDIOD0
TRDGRC0 TRDBFC0 = 0 (Not used in reset synchronous PWM mode.) —
TRDGRD0 TRDBFC0 = 0
TRDGRA1 — General register. Set the changing point of PWM2 output. TRDIOA1
TRDIOC1
TRDGRB1 — General register. Set the changing point of PWM3 output. TRDIOB1
TRDIOD1
TRDGRC1 TRDBFC1= 0 (Not used in reset synchronous PWM mode.) —
TRDGRD1 TRDBFD1 = 0
TRDGRC0 TRDBFC0 = 1 Buffer register. Set the next PWM period
(see 8. 3. 1 (2) Buffer Operation).
(TRDIOC0, output
inverted every
PWM period)
TRDGRD0 TRDBFD0 = 1 Buffer register. Set the changing point of the next PWM1
(see 8. 3. 1 (2) Buffer Operation).
TRDIOB0
TRDIOD0
TRDGRC1 TRDBFC1 = 1 Buffer register. Set the changing point of the next PWM2
(see 8. 3. 1 (2) Buffer Operation).
TRDIOA1
TRDIOC1
TRDGRD1 TRDBFD1 = 1 Buffer register. Set the changing point of the next PWM3
(see 8. 3. 1 (2) Buffer Operation).
TRDIOB1
TRDIOD1
Caution When the setting of bits TCK2 to TCK0 in the TRDCR0 register is 000B (f
CLK, fIH, fPLL, fSUB, and fIL) and
the compare value is set to 0000H, a request signal to the data transfer controller (DTC) and the event
link controller (ELC) is generated only once immediately after the count starts. When the compare
value is 0001H or higher, a request signal is generated each time a compare match occurs.
Remark i = 0 or 1, j = A, B, C, or D
TRDBFC0, TRDBFD0, TRDBFC1, TRDBFD1: Bits in TRDMR register
To Next Page
Loading...
Need help?
General
