Renesas RL78/F14

RL78/F13, F14 CHAPTER 12 A/D CONVERTER
R01UH0368EJ0210 Rev.2.10 713
Dec 10, 2015
Table 12-3. A/D Conversion Time Selection (3/4)
(3) 4.0 V  V
DD  5.5 V
When there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode)
A/D Converter Mode
Register 0 (ADM0)
Mode Conversion
Clock (f
AD)
Number of
conversion
clocks
Conversion
Time
Conversion Time Selection
FR2 FR1 FR0 LV1 LV0 fCLK =
1 MHz
fCLK =
2 MHz
fCLK =
4 MHz
fCLK =
8 MHz
fCLK =
16 MHz
fCLK =
32 MHz
0 0 0 0 0 Normal
1
fCLK/64
19 f
AD
(number of
sampling
clocks: 7
f
AD)
1216/f
CLK Setting
prohibite
d
Setting
prohibite
d
Setting
prohibite
d
Setting
prohibite
d
Setting
prohibite
d
38 s
0 0 1 fCLK/32 608/fCLK 38 s 19 s
0 1 0 fCLK/16 304/fCLK 38 s 19 s 9.5 s
0 1 1 fCLK/8 152/fCLK 38 s 19 s 9.5 s 4.75 s
1 0 0 fCLK/6 114/fCLK 28.5 s 14.25 s 7.125 s 3.5625
s
1 0 1 fCLK/5 95/fCLK 23.75 s 11.875
s
5.938 s 2.9688
s
1 1 0 fCLK/4 76/fCLK 38 s 19 s 9.5 s 4.75 s 2.375 s
1 1 1 fCLK/2 38/fCLK 38 s 19 s 9.5 s 4.75 s 2.375 s Setting
prohibite
d
0 0 0 0 1 Normal
2
fCLK/64
17 f
AD
(number of
sampling
clocks: 5
f
AD)
1088/f
CLK Setting
prohibite
d
Setting
prohibite
d
Setting
prohibite
d
Setting
prohibite
d
Setting
prohibite
d
34 s
0 0 1 fCLK/32 544/fCLK 34 s 17 s
0 1 0 fCLK/16 272/fCLK 34 s 17 s 8.5 s
0 1 1 fCLK/8 136/fCLK 34 s 17 s 8.5 s 4.25 s
1 0 0 fCLK/6 102/fCLK 25.5 s 12.75 s 6.375 s 3.1875
s
1 0 1 fCLK/5 85/fCLK 21.25 s 10.625
s
5.3125
s
2.6563
s
1 1 0 fCLK/4 68/fCLK 34 s 17 s 8.5 s 4.25 s 2.125 s
Note
1 1 1 fCLK/2 34/fCLK 34 s 17 s 8.5 s 4.25 s 2.125 s
Note
Setting
prohibite
d
Other than above Setting prohibited
Note This value is prohibited when using the temperature sensor.
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the same data, stop A/D conversion
once (ADCS = 0) beforehand.
2. The above conversion time does not include clock frequency errors. Select conversion time, taking
clock frequency errors into consideration.
3. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit
resolution is selected, the values are shorter by two cycles of the conversion clock (f
AD).
Remark f
CLK: CPU/peripheral hardware clock frequency