RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 798
Dec 10, 2015
Figure 15-1 shows the block diagram of the serial array unit 0.
Figure 15-1. Block Diagram of Serial Array Unit 0
Caution: If operation is stopped (SEmn = 0), the upper 7 bits set the clock division, and the lower bits have
no meaning.
If operation is in progress (SEmn = 1), the serial data register 10 functions as the buffer register.
PRS
013
4
PRS
003
PRS
012
PRS
011
PRS
010
PRS
002
PRS
001
PRS
000
4
f
CLK
f
CLK
/2
0
to f
CLK
/2
11
f
CLK
/2
0
to f
CLK
/2
11
CKS00
MD001CCS00
STS00 MD002
00
SOE01
SOE00
PM30
SSIE00
SAU0EN
0
0
SE01 SE00
0
0
ST01 ST00
0
0
SS01
SS00
TXE
00
RXE
00
DAP
00
CKP
00
0
PECT
00
OVCT
00
PTC
001
SLC
000
PTC
000
DIR
00
SLC
001
DLS
001
DLS
000
TSF
00
OVF
00
BFF
00
PEF
00
CK01
CK00
f
MCK
fTCLK
f
SCK
CK01
CK00
SNFEN
00
SNFEN00
PMxx
0
0
SOL01 SOL00
00
CKO01 CKO00
00
SO01
SO00
0
0
0
0
0
0
00
Serial output
enable register 0
(SOE0)
Serial channel
enable status
register 0 (SE0)
Serial channel
stop register 0
(ST0)
Serial channel
start register 0
(SS0)
Noise filter enable
register 0 (NFEN0)
Serial output level
register 0 (SOL0)
Serial output register 0 (SO0)
Serial clock select register 0 (SPS0)
Selector
Selector
Peripheral enable
register 0 (PER0)
Prescaler
Shift register
Serial data register 00 (SDR00)
(Buffer register block)
(Clock division setting block)
Output latch
(Pxx)
Selector
Clock controller
Selector
Interrupt
controller
Output
controller
Communication controller
Serial flag clear trigger
register 00 (SIR00)
Communication
status
Error
information
Clear
Serial status register 00 (SSR00)
Error controller
Edge/level
detection
Edge
detection
Serial communication operation setting register 00 (SCR00)
When UART0
Serial mode register 00 (SMR00)
Communication controller
Edge/level
detection
Output latch
(P30)
Mode selection
CSI00 or IIC00
or UART0
(for transmission)
Serial data output pin
(when CSI00: SO00)
(when IIC00: SDA00)
(when UART0: T
X
D0)
Serial transfer end interrupt
(when CSI00: INTCSI00)
(when IIC00: INTIIC00)
(when UART0: INTST0)
Edge
detection
Serial clock I/O pin
(when CSI00: SCK00)
(when IIC00: SCL00)
Serial data input pin
(when CSI00: SI00)
(when IIC00: SDA00)
(when UART0: RxD0)
Slave selection
input pin
(when CSI00: SSI00)
Input switch control
register (ISC)
Serial transfer end interrupt
(when CSI01: INTCSI01)
(when IIC01: INTIIC01)
(when UART0: INTSR0)
Mode selection
CSI01 or IIC01
or UART0
(for reception)
Serial data output pin
(when CSI01: SO01)
(when IIC01: SDA01)
Serial data input pin
(when CSI01: SI01)
(when IIC01: SDA01)
Serial clock I/O pin
(when CSI01: SCK01)
(when IIC01: SCL01)
Selector
Noise
elimination
enabled/
disabled
Synchro-
nous
circuit
Synchro-
nous
circuit
Synchro-
nous
circuit
Channel 0
(LIN-bus supported)
Channel 1
(LIN-bus supported)
0
0
SSE01 SSE00
Serial slave select
enable register 0 (SSE0)
Slave select input pin
(when CSI01: SSI01)
Note
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