RL78/F13, F14 CHAPTER 15 SERIAL ARRAY UNIT
R01UH0368EJ0210 Rev.2.10 915
Dec 10, 2015
(4) Processing flow (in continuous reception mode)
Figure 15-88. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
Caution The MDmn0 bit can be rewritten even during operation.
However, rewrite it before receive of the last bit is started, so that it has been rewritten before the
transfer end interrupt of the last receive data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 15-89 Flowchart of Master Reception
(in Continuous Reception Mode).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1), p: CSI number (p = 00, 01, 10, 11),
mn = 00, 01, 10, 11
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
Shift
register mn
INTCSIp
TSFmn
Reception & shift operation
Reception & shift operation
BFFmn
Reception & shift operation
MDmn0
Data reception (8-bit length)
Data reception (8-bit length)
Data reception (8-bit length)
STmn
<4> <5>
Dummy data Dummy data
Receive data 3
Write
Read
Read
Read
Write
<1>
<2>
<3>
<2>
<3>
<4> <2>
<7> <8>
Dummy data
Write
<6>
<3>
Receive data 2
Receive data 1
Receive data 1
Receive data 2
Receive data 3
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