2212
Service Manual
Digital Circuitry
8 Bit wide devices are used
as
processor memory:
the
static RAM's U1804
and U1805 and
the
ROM's U1806 and U1807.
In the standard version, RAM's of 32k x 8
and
ROM's of 128k x 8 are used.
Parts of
the
databus are buffered
by
U1850
and
U2103 (diagram 21).
To generate a timing signal
for
operating these bus-buffers (BUFGATE_0),
and for generation of waitstates
(DTACK_0,
U1801
pin
24), the circuitry
drawn below U1812 is added.
All memory operations are performed with no waitstates, except for the
timing of the TMS 9914A
GPIB
chip,
which
requires
an
additional waitstate
(68 nsec).
The crystal determining the processor speed is Y1800 (29.4912 MHz). This
makes the microprocessor clock
(CLKOUT
pin
29)
run
at 14.7456 MHz. This
frequency is
fed
to the counter U1840
which
divides this frequency down to
4.9152 MHz. This signal
(XCKI)
is fed back to the 68070 to generate proper
UART timing and to the display system as signal
CLK5M.
The 24C04
EEROM
U1800 which is connected with the 68070 through an I
2
C
bus contains the calibration values of the instrument
and
the
menu
settings.
The device is placed on the A10 board to keep the calibration data
with
the
analog circuitry. Activity at the
I2C
bus can only be seen at power up, when the
contents of the
EEROM
are copied into
RAM,
or
when settings are saved
(at
menu exit etc.).
The
+5VD
supply voltage is monitored by U1802 to generate proper
RESET_O
timing. The level of the
RESET
_0 line can be monitored by watching DS2100
(diagram
21);
when
this
LED
is lit, a reset is generated.
Input-Output operation with other circuitry is done
with
latches, connected
straight to the databus and memory mapped
in
the 68070 memory map.
U1830 enables the microprocessor to read settings from the analog mainboard
A10
and
the front panel board A12.
Through U1860 the microprocessor can control both boards. The A10 analog
board has two major control mechanisms, which are both driven by the 68070
microprocessor on A15: the daculator and the shift register chain. They
are
both
controlled serially, and use the same clock and data lines
(SER_CLK
and
SER_DAT
A).
Two separate load pulses at the end of a transfer determine which
devices are addressed
(CHAIN_LD
and
DACU_LD).
Updates of the daculator can
be expected when an analog control setting is changed. A
CHAlN_LD
pulse can
be seen when sensitivity settings etc. are changed that need update of relays- or
trigger settings.
Communication with the front panel processor is done through a bidirectional
synchronous exchange of 8 bytes. The clock
(FP
_CLCK)
is generated
by
the
68070 processor. Data is sent from A10
to
the front panel board through the
FP
_SDI
line, while simultaneously 8 bits from the front panel are transmitted to
the 68070 processor across the
FP
_SD0
line. This transfer basically occurs every
two milliseconds.
3-
21
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