2212 Service Manual
Record Mode Acquisition
Acquiring Record Mode Data
Digital Circuitry
The
12 address lines (ACQA0 - ACQA11) of the acquisition RAM's U1605
and
U1606 are driven
by
the address counters U1615, U1616
and
U1617,
which
are clocked by
RECCLK.
The
WRCLK_0
and
RECCLK
signals are both
at
the
same rate as
SA
VCLK_0.
For each SA
VCLK_0,
a
new
address is generated for the next acquisition.
Before every acquisition, the address counter is pre-loaded
with
a value
which
is
25
or 75% of the record length determined by the SPT signal (Ul
705
pt2). As soon as the acquisition
RAM
has
been
filled
with
enough data, the
PREFUL signal is generated from flip-flop U1621.
The
state machine U1610
and
U1611 will
then
activate TRIGENA, enabling
the
trigger signal from the
A10 board. When a trigger occurs through this SWPGT_0 line, flip-flop
Ul
718 will be set and make the
TRIGO
line
"1
".
Immediately the
RCENA
signal will be set high to enable the post trigger
counter U1618, U1619
and
U1620, which was pre-loaded also.
When
the
post trigger data is acquired, this counter will generate
EOR
(End
Of Record) through U1621 pt5.
EOR
will immediately stop
RECCLK,
and
therefore the acquisition,
at
the
AND
gate U1622B.
Record Mode Data Transfer to 68070.
The state machine U1610 and U1611 will request for OMA as soon as
EOR
is
detected by pulsing the OMASET _0 line low, and
in
that way activating the
REQ2_0 line. Also the output enables
of
U1603
and
U1604
will
be made
inactive to free
the
ACQO[0
..
15] acquisition databus. The 68070
microprocessor
will
then
start a OMA-in transfer from acquisition
RAM
to
system memory
in
cycle-stealing mode (one word at a time).
Handshaking is done by ACK2_0
and
REQ2_0 microprocessor lines, and the
ACK2_0 line also controls the output enable of the latches
01607
and U1608
which
connect
it
to the microprocessor databus.
Note,
that
because of a 16 bit wide bus is used, channel 1
and
channel 2 data
is simultaneously transferred as two bytes
in
a 16 bits word. Because the
acquisition was stopped immediately after
EOR,
the
address on ACQA(0-11]
is automatically the first position
in
the
record that is acquired
in
the
acquisition
RAM.
The software will determine
the
length of
the
OMA
transfer(= record length). The speed of
the
transfer is limited by
the
state machine using a 500 kHz clock.
After
the
OMA
transfer
the
microprocessor will reset
the
acquisition logic
through pulsing ACQRST_0 low, and start the procedure all over again.
The connection of the acquisition data to the system memory, has been
designed in such a way that acquisition records
can
be written to the display
hardware without software modification, thus enabling fast acquisition
update rates.
3-
27
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