Digital Circuitry
REQ2_0
ACK2_0
Connections
with
Acquisition
System
3-
20
OMA channel 2
UART
RXD
TXD
SCC68070
Microprocessor
Address Bus
PROA[1
..
23]
System
ROM
128k X 16
Databus
PROD[0
..
15]
REQ1_0
MA channel 1
ACK1_0
12c
bus
Connections
with
Display
System
System
RAM
32k
X 16
Connections with the parallel interface,
and optional wih the RS232 and GPIB
interface boards
Connections
with
Analog Mainboard and Frontpanel
Figure 3-5: 68070 Micro Proces.sor Block Diagram
The
68070
processor is capable
of
performing byte
wide
operations
which
is done with the
ODS_O
and
LDS_O
lines selecting the
upper
or
lower part of the databus separately
when
needed.
Address decoding is done by IC's
01810,
01811
and
U1812.
The
lower
half
of the
16
MByte addressing range is divided
in
8 parts of 1 MByte.
U1810
decodes these 8 memory banks unconditionally,
01811
decodes
as additional condition that the
upper
part of the databus is selected and
U1812
decodes the lower databus operations.
Theory
of
Operation
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