Video Option
Counting the Number
of
Lines in a Video System
(Diagram 27)
3-
40
Besides the combinatorial logic, U2708 also contains a state machine.
With STRTCNT,
the
main
controller initiates the state machine.
The
statemachine resets
the
line
counter (U2712), sets U2713
and
U2714
in
parallel load mode
and
waits for
the
next field pulse.
The
HCLK
pulses are
passed
on
to U2712 (HCNT) until the next field pulse.
Then
the
counting
process stops,
and
the
VALID signal asserts.
The
last
bit
in
the shift register U2714 is transparent, so
the
processor
can
poll
VALID
at U2714
pin
9 ( CHAIN_RET). The controller sets STRTCNT to
0 to tell the state
machine
that
the
result will be retrieved. U2713
and
U2714 are set
in
serial shift
mode
and
the processor clocks
the
result to
the
processor board.
Revised 3/93 Theory
of
Operation
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