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Watchdog Timer Register
WDCTL (0xC9) – Watchdog Timer Control
Bit Name Reset R/W Description
7:4
CLR[3:0]
0000 R0/W Clear timer. In watchdog mode, when 0xA followed by 0x5 is written to these bits, the timer is
cleared (i.e. loaded with 0). Note that the timer is only cleared when 0x5 is written within one
watchdog clock period after 0xA was written. Writing these bits when the Watchdog Timer is IDLE
has no effect. When operating in timer mode, the timer can be cleared to 0x0000 (but not stopped)
by writing 1 to CLR[0] (the other 3 bits are don't care).
3:2
MODE[1:0]
00 R/W Mode select. These bits are used to start the WDT in watchdog mode or timer mode. Setting these
bits to IDLE stops the timer when in timer mode. Note: to switch to watchdog mode when operating
in timer mode, first stop the WDT - then start the WDT in Watchdog mode. When operating in
Watchdog mode, writing these bits has no effect.
00: IDLE
01: Reserved
10: Watchdog mode
11: Timer mode
1:0
INT[1:0]
00 R/W Timer interval select. These bits select the timer interval, which is defined as a given number of
32-kHz oscillator periods. Note that the interval can only be changed when the WDT is IDLE, so the
interval must be set at the same time as the timer is started.
00: Clock period × 32,768 (~1 s) when running the 32-kHz XOSC
01: Clock period × 8192 (~0.25 s)
10: Clock period × 512 (~15.625 ms)
11: Clock period × 64 (~1.9 ms)
For CC253x and CC2540, when clock division is enabled through CLKCONCMD.CLKSPD, the
length of the watchdog timer interval is reduced by a factor equal to the current oscillator clock
frequency divided by the set clock speed. E.g., if 32-MHz crystal is selected and clock speed is set
to 4 MHz, then the watchdog timeout is reduced by a factor o 32 MHz/4 MHz = 8. If the watchdog
interval set by WDCTL.INT was 1 s, nominally it is 1/8 s with this clock division factor. For CC2541,
the watchdog timer interval is independent of the clock division rate.
161
SWRU191C–April 2009–Revised January 2012 Watchdog Timer
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