Memory
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Table 2-1. SFR Overview (continued)
Register SFR
Module Description
Name Address
T3CC1 0xCF Timer 3 Timer 3 channel 1 compare value
T4CNT 0xEA Timer 4 Timer 4 counter
T4CTL 0xEB Timer 4 Timer 4 control
T4CCTL0 0xEC Timer 4 Timer 4 channel 0 compare control
T4CC0 0xED Timer 4 Timer 4 channel 0 compare value
T4CCTL1 0xEE Timer 4 Timer 4 channel 1 compare control
T4CC1 0xEF Timer 4 Timer 4 channel 1 compare value
TIMIF 0xD8 TMINT Timers 1/3/4 joint interrupt mask/flags
U0CSR 0x86 USART 0 USART 0 control and status
U0DBUF 0xC1 USART 0 USART 0 receive/transmit data buffer
U0BAUD 0xC2 USART 0 USART 0 baud-rate control
U0UCR 0xC4 USART 0 USART 0 UART control
U0GCR 0xC5 USART 0 USART 0 generic control
U1CSR 0xF8 USART 1 USART 1 control and status
U1DBUF 0xF9 USART 1 USART 1 receive/transmit data buffer
U1BAUD 0xFA USART 1 USART 1 baud-rate control
U1UCR 0xFB USART 1 USART 1 UART control
U1GCR 0xFC USART 1 USART 1 generic control
WDCTL 0xC9 WDT Watchdog Timer control
34
8051 CPU SWRU191C–April 2009–Revised January 2012
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