Chapter 8
SWRU191C–April 2009– Revised January 2012
DMA Controller
The Direct Memory Access (DMA) Controller can be used to relieve the 8051 CPU core of handling data
movement operations, thus achieving high overall performance with good power efficiency. The DMA
controller can move data from a peripheral unit such as ADC or RF transceiver to memory with minimum
CPU intervention.
The DMA controller coordinates all DMA transfers, ensuring that DMA requests are prioritized
appropriately relative to each other and to CPU memory access. The DMA controller contains a number of
programmable DMA channels for memory-memory data movement.
The DMA controller controls data transfers over the entire address range in XDATA memory space.
Because most of the SFR registers are mapped into the DMA memory space, these flexible DMA
channels can be used to unburden the CPU in innovative ways, e.g., to feed a USART with data from
memory or periodically to transfer samples between ADC and memory, etc. Use of the DMA can also
reduce system power consumption by keeping the CPU in a low-power mode without having to wake up to
move data to or from a peripheral unit (see Section 4.1.1 for CPU low-power mode). Note that
Section 2.2.3 describes the SFR registers that are not mapped into XDATA memory space.
The main features of the DMA controller are as follows:
• Five independent DMA channels
• Three configurable levels of DMA channel priority
• 32 configurable transfer trigger events
• Independent control of source and destination address
• Single, block and repeated transfer modes
• Supports length field in transfer data, setting variable transfer length
• Can operate in either word-size or byte-size mode
Topic ........................................................................................................................... Page
8.1 DMA Operation ................................................................................................. 96
8.2 DMA Configuration Parameters ........................................................................... 98
8.3 DMA Configuration Setup ................................................................................. 100
8.4 Stopping DMA Transfers .................................................................................. 101
8.5 DMA Interrupts ................................................................................................ 101
8.6 DMA Configuration Data Structure ..................................................................... 101
8.7 DMA Memory Access ....................................................................................... 101
8.8 DMA Registers ................................................................................................ 104
95
SWRU191C–April 2009–Revised January 2012 DMA Controller
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