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Endpoints 1–5
21.7.3 FIFO Access
The endpoint FIFOs are accessed by reading and writing to the registers USBF0–USBF6. Writing to a
register causes the byte written to be inserted into the IN FIFO. Reading a register causes the next byte in
the OUT FIFO to be extracted and the value of this byte to be returned.
When a data packet has been written to an IN FIFO, the USBCSIL.INPKT_RDY bit must be set to 1. If
double buffering is enabled, the USBCSIL.INPKT_RDY bit is cleared immediately after it has been written,
and another data packet can be loaded. This does not generate an IN endpoint interrupt, because an
interrupt is only generated when a packet has been sent. When double buffering is used, firmware should
check the status of the USBCSIL.PKT_PRESENT bit before writing to the IN FIFO. If this bit is 0, two data
packets can be written. Double-buffered isochronous endpoints should only load two packets the first time
the IN FIFO is loaded. After that, one packet is loaded for every USB frame. To send a zero-length data
packet, USBCSIL.INPKT_RDY should be set to 1 without loading a data packet into the IN FIFO.
A data packet can be read from the OUT FIFO when the USBCSOL.OUTPKT_RDY bit is 1. An interrupt is
generated when this occurs, if enabled. The size of the data packet is kept in the USBCNTH:USBCNTL
registers. Note that this value is only valid when USBCSOL.OUTPKT_RDY = 1. When the data packet has
been read from the OUT FIFO, the USBCSOL.OUTPKT_RDY bit must be cleared. If double buffering is
enabled, there may be two data packets in the FIFO. If another data packet is ready when the
USBCSOL.OUTPKT_RDY bit is cleared, the USBCSOL.OUTPKT_RDY bit is asserted immediately, and an
interrupt is generated (if enabled) to signal that a new data packet has been received. The
USBCSOL.FIFO_FULL bit is set when there are two data packets in the OUT FIFO.
The AutoClear feature is supported for OUT endpoints. When enabled, the USBCSOL.OUTPKT_RDY bit is
cleared automatically when USBMAXO bytes have been read from the OUT FIFO. The AutoClear feature is
enabled by setting USBCSOH.AUTOCLEAR = 1. The AutoClear feature can be used to reduce the time the
data packet occupies the OUT FIFO buffer and is typically used for bulk endpoints.
A complementary AutoSet feature is supported for IN endpoints. When enabled, the
USBCSIL.INPKT_RDY bit is set automatically when USBMAXI bytes have been written to the IN FIFO.
The AutoSet feature is enabled by setting USBCSIH.AUTOSET =
1. The AutoSet feature can reduce the overall time it takes to send a data packet and is
typically used for bulk endpoints.
21.7.4 Endpoint 1–5 Interupts
The following events may generate an IN EPx interrupt request (x indicates the endpoint number):
• A data packet that was loaded into the IN FIFO has been sent to the USB host.
(USBCSIL.INPKT_RDY should be set to 1 when a new packet is ready to be transferred. This bit is
cleared by hardware when the data packet has been sent.)
• A STALL has been sent (USBCSIL.SENT_STALL
= 1). Only bulk/interrupt endpoints can be stalled
• The IN FIFO is flushed due to the USBCSIH.FLUSH_PACKET bit being set to 1.
Any of these events causes USBIIF.INEPxIF to be asserted, regardless of the status of the IN EPx
interrupt mask bit USBIIE.INEPxIE. If the IN EPx interrupt mask bit is set to 1, the CPU interrupt flag
IRCON2.P2IF is also asserted. An interrupt request is only generated if IEN2.P2IE and
USBIIE.INEPxIE are both set to 1. The x in the register name refers to the endpoint number, 1–5)
The following events may generate an OUT EPx interrupt request:
• A data packet has been received (USBCSOL.OUTPKT_RDY = 1).
• A STALL has been sent (USBCSIL.SENT_STALL
= 1). Only bulk/interrupt endpoints can be stalled.
Any of these events causes USBOIF.OUTEPxIF to be asserted, regardless of the status of the OUT EPx
interrupt mask bit USBOIE.OUTEPxIE. If the OUT EPx interrupt mask bit is set to 1, the CPU interrupt flag
IRCON2.P2IF is also asserted. An interrupt request is only generated if IEN2.P2IE and
USBOIE.OUTEPxIE are both set to 1.
197
SWRU191C–April 2009–Revised January 2012 USB Controller
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