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Table 2-1. SFR Overview (continued)
Register SFR
Module Description
Name Address
DPH1 0x85 CPU Data pointer 0 high byte
PCON 0x87 CPU Power mode control
TCON 0x88 CPU Interrupt flags
P1 0x90 CPU Port 1. Readable from XDATA (0x7090)
DPS 0x92 CPU Data pointer select
S0CON 0x98 CPU Interrupt flags 2
IEN2 0x9A CPU Interrupt enable 2
S1CON 0x9B CPU Interrupt flags 3
P2 0xA0 CPU Port 2. Readable from XDATA (0x70A0)
IEN0 0xA8 CPU Interrupt enable 0
IP0 0xA9 CPU Interrupt priority 0
IEN1 0xB8 CPU Interrupt enable 1
IP1 0xB9 CPU Interrupt priority 1
IRCON 0xC0 CPU Interrupt flags 4
PSW 0xD0 CPU Program status Word
ACC 0xE0 CPU Accumulator
IRCON2 0xE8 CPU Interrupt flags 5
B 0xF0 CPU B register
DMAIRQ 0xD1 DMA DMA interrupt flag
DMA1CFGL 0xD2 DMA DMA channel 1–4 configuration address low
DMA1CFGH 0xD3 DMA DMA channel 1–4 configuration address high
DMA0CFGL 0xD4 DMA DMA channel 0 configuration address low
DMA0CFGH 0xD5 DMA DMA channel 0 configuration address high
DMAARM 0xD6 DMA DMA channel armed
DMAREQ 0xD7 DMA DMA channel start request and status
— 0xAA — Reserved
— 0x8E — Reserved
— 0x99 — Reserved
— 0xB0 — Reserved
— 0xB7 — Reserved
— 0xC8 — Reserved
P0IFG 0x89 IOC Port 0 interrupt status flag
P1IFG 0x8A IOC Port 1 interrupt status flag
P2IFG 0x8B IOC Port 2 interrupt status flag
PICTL 0x8C IOC Port pins interrupt mask and edge
P0IEN 0xAB IOC Port 0 interrupt mask
P1IEN 0x8D IOC Port 1 interrupt mask
P2IEN 0xAC IOC Port 2 interrupt mask
P0INP 0x8F IOC Port 0 input mode
PERCFG 0xF1 IOC Peripheral I/O control
APCFG 0xF2 IOC Analog peripheral I/O configuration
P0SEL 0xF3 IOC Port 0 function select
P1SEL 0xF4 IOC Port 1 function select
P2SEL 0xF5 IOC Port 2 function select
P1INP 0xF6 IOC Port 1 input mode
P2INP 0xF7 IOC Port 2 input mode
P0DIR 0xFD IOC Port 0 direction
32
8051 CPU SWRU191C–April 2009–Revised January 2012
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