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Flash DMA Trigger
6.3.1 Performing Flash Erase From Flash Memory
Note that while executing program code from within flash memory, when a flash erase or write operation is
initiated the CPU stalls, and program execution resumes from the next instruction when the flash controller
has completed the operation.
The following code example of how to erase one flash page in the CC2530 is given for use with the IAR
compiler:
#include <ioCC2530.h>
unsigned char erase_page_num = 3; /* page number to erase, here: flash page #3 */
/* Erase one flash page */
EA = 0; /* disable interrupts */
while (FCTL & 0x80); /* poll FCTL.BUSY and wait until flash controller is ready */
FADDRH = erase_page_num << 1; /* select the flash page via FADDRH[7:1] bits */
FCTL |= 0x01; /* set FCTL.ERASE bit to start page erase */
while (FCTL & 0x80); /* optional: wait until flash write has completed (~20 ms) */
EA = 1; /* enable interrupts */
6.3.2 Different Flash Page Size on CC2533
The flash page size has been reduced from 2 KB (2048 bytes) on CC2530/CC2531/CC2540/CC2541 to 1
KB (1024 bytes) on CC2533. When performing page-erase operations on the flash memory, the page to
be erased is addressed with the register bits FADDRH[6:0] on CC2533 as opposed to FADDRH[7:1] on
CC2530/CC2531/CC2540. The page lock bits are still placed in the upper 16 bytes of the last accessible
flash page.
6.4 Flash DMA Trigger
The flash DMA trigger is activated when flash data written to the FWDATA register has been written to the
specified location in the flash memory, thus indicating that the flash controller is ready to accept new data
to be written to FWDATA. Four trigger pulses are generated. In order to start the first transfer, one must set
the FCTL.WRITE bit to 1. The DMA and the flash controller then handle all transfers automatically for the
defined block of data (LEN in DMA configuration). It is further important that the DMA is armed prior to
setting the FCTL.WRITE bit, that the trigger source is set to FLASH (TRIG[4:0] = 10010), and that
the DMA has high priority so the transfer is not interrupted. If interrupted for more than 20 μs, the write
operation times out and FCTL.WRITE bit is cleared.
6.5 Flash Controller Registers
The flash controller registers are described in this section.
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SWRU191C–April 2009–Revised January 2012 Flash Controller
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