DMA Operation
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8.1 DMA Operation
There are five DMA channels available in the DMA controller, numbered channel 0 through channel 4.
Each DMA channel can move data from one place within the DMA memory space to another, i.e.,
between XDATA locations.
In order to use a DMA channel, it must first be configured as described in Section 8.2 and Section 8.3.
Figure 8-1 shows the DMA state diagram.
Once a DMA channel has been configured, it must be armed before any transfers are allowed to be
initiated. A DMA channel is armed by setting the appropriate bit in the DMA channel-arm register DMAARM.
When a DMA channel is armed, a transfer begins when the configured DMA trigger event occurs. Note
that the time to arm one channel (i.e., get configuration data) takes nine system clocks; thus, if the
corresponding DMAARM bit is set and a trigger appears within the time it takes to configure the channel, the
wanted trigger is lost. If two or more DMA channels are armed simultaneously, the time for all channels to
be configured is longer (sequential read from memory). If all five are armed, it takes 45 system clocks, and
channel 1 is ready first, then channel 2, and lastly channel 0 (all within the last eight system clocks). There
are 32 possible DMA trigger events (see Table 8-1), e.g., UART transfer, timer overflow. The trigger event
to be used by a DMA channel is set by the DMA channel configuration; thus, no knowledge of this is
available until after the configuration has been read. The DMA trigger events are listed in Table 8-1.
In addition to starting a DMA transfer through the DMA trigger events, the user software may force a DMA
transfer to begin by setting the corresponding DMAREQ bit.
It should be noted that if the previously configured trigger source generates trigger events while DMA is
being configured, these are counted as missed events, and as soon as the DMA channel is ready, the
transfer is started. This occurs even though the new trigger source is not the same as the previous one. In
some situations, this leads to errors in the transfer. In order to account for this, trigger source 0 should be
the source between reconfigurations. This is achieved by setting up dummy source and destination
addresses, using fixed length of one byte, block transfer, and trigger source 0. Enabling a software trigger
(DMAREQ) clears missed-trigger counting, and no new triggers are generated while a new configuration is
fetched from memory (unless software writes to DMAREQ for this channel).
A DMAREQ bit is cleared only when the corresponding DMA transfer occurs. The DMAREQ bit is not cleared
when the channel is disarmed.
96
DMA Controller SWRU191C– April 2009–Revised January 2012
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