www.ti.com
Timer 1 Registers
T1STAT (0xAF) – Timer 1 Status
Bit Name Reset R/W Description
7:6 – 00 R0 Reserved
5
OVFIF
0 R/W0 Timer 1 counter-overflow interrupt flag. Set when the counter reaches the terminal count value in
free-running or modulo mode, and when zero is reached counting down in up-down mode. Writing a 1
has no effect.
4
CH4IF
0 R/W0 Timer 1 channel 4 interrupt flag. Set when the channel 4 interrupt condition occurs. Writing a 1 has no
effect.
3
CH3IF
0 R/W0 Timer 1 channel 3 interrupt flag. Set when the channel 3 interrupt condition occurs. Writing a 1 has no
effect.
2
CH2IF
0 R/W0 Timer 1 channel 2 interrupt flag. Set when the channel 2 interrupt condition occurs. Writing a 1 has no
effect.
1
CH1IF
0 R/W0 Timer 1 channel 1 interrupt flag. Set when the channel 1 interrupt condition occurs. Writing a 1 has no
effect.
0
CH0IF
0 R/W0 Timer 1 channel 0 interrupt flag. Set when the channel 0 interrupt condition occurs. Writing a 1 has no
effect.
T1CCTL0 (0xE5) – Timer 1 Channel 0 Capture/Compare Control
Bit Name Reset R/W Description
7
RFIRQ
0 R/W When set, use RF interrupt for capture instead of regular capture input.
6
IM
1 R/W Channel 0 interrupt mask. Enables interrupt request when set.
5:3
CMP[2:0]
000 R/W Channel 0 compare-mode select. Selects action on output when timer value equals compare value in
T1CC0
000: Set output on compare
001: Clear output on compare
010: Toggle output on compare
011: Set output on compare-up, clear on 0
100: Clear output on compare-up, set on 0
101: Reserved
110: Reserved
111: Initialize output pin. CMP[2:0] is not changed.
2
MODE
0 R/W Mode. Select Timer 1 channel 0 capture or compare mode
0: Capture mode
1: Compare mode
1:0
CAP[1:0]
00 R/W Channel 0 capture-mode select
00: No capture
01: Capture on rising edge
10: Capture on falling edge
11: Capture on all edges
T1CC0H (0xDB) – Timer 1 Channel 0 Capture/Compare Value, High
Bit Name Reset R/W Description
7:0
T1CC0[15:8]
0x00 R/W Timer 1 channel 0 capture/compare value high-order byte. Writing to this register when
T1CCTL0.MODE = 1 (compare mode) causes the T1CC0[15:0] update to the written value to be
delayed until T1CNT = 0x0000.
T1CC0L (0xDA) – Timer 1 Channel 0 Capture/Compare Value, Low
Bit Name Reset R/W Description
7:0
T1CC0[7:0]
0x00 R/W Timer 1 channel 0 capture/compare value low-order byte. Data written to this register is stored
in a buffer but not written to T1CC0[7:0] until, and at the same time as, a later write to T1CC0H
takes effect.
119
SWRU191C–April 2009–Revised January 2012 Timer 1 (16-Bit Timer)
Submit Documentation Feedback
Copyright © 2009–2012, Texas Instruments Incorporated