Timer Operation
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22.1 Timer Operation
This section describes the operation of the timer.
22.1.1 General
After a reset, the timer is in the timer IDLE mode, where it is stopped. The timer starts running when
T2CTRL.RUN is set to 1. The timer then enters the timer RUN mode. Either the entry is immediate, or it is
performed synchronously with the 32-kHz clock. See Section 22.4 for a description of the synchronous
start and stop mode.
Once the timer is running in RUN mode, it can be stopped by writing a 0 to T2CTRL.RUN. The timer then
enters the timer IDLE mode. The stopping of the timer is performed either immediately or synchronously
with the 32-kHz clock.
22.1.2 Up Counter
Timer 2 contains a 16-bit timer, which increments on each clock cycle. The counter value can be read
from registers T2M1:T2M0 with register T2MSEL.T2MSEL set to 000. Note that the register content in
T2M1 is latched when T2M0 is read, meaning that T2M0 must always be read first.
When the timer is idle, the counter can be modified by writing to registers T2M1:T2M0 with register
T2MSEL.T2MSEL set to 000. T2M0 must be written first.
22.1.3 Timer Overflow
At the same time as the timer counts to a value that is equal to the set timer period, a timer overflow
occurs. When the timer overflow occurs, the timer is set to 0x0000. If the overflow interrupt mask bit
T2IRQM.TIMER2_PERM is 1, an interrupt request is generated. The interrupt flag bit
T2IRQF.TIMER2_PERF is set to 1, regardless of the interrupt mask value.
22.1.4 Timer Delta Increment
The timer period may be adjusted once during a timer period by writing a timer delta value. When the
timer is running and a timer delta value is written to multiplexed registers T2M1:T2M0 with
T2MSEL.T2MSEL set to 000, the 16-bit timer halts at its current value and a delta counter starts counting.
The T2M0 register must be written before T2M1. The delta counter starts counting from the delta value
written, down to zero. Once the delta counter reaches zero, the 16-bit timer starts counting again.
The delta counter decrements at the same rate as the timer. When the delta counter has reached zero, it
does not start counting again until a delta value is written once again. In this way, a timer period may be
increased by the delta value in order to make adjustments to the timer overflow events over time.
22.1.5 Timer Compare
A timer compare occurs at the same time as the timer counts to a value that is equal to one of the 16-bit
compare values set. When a timer compare occurs, the interrupt flag T2IRQF.TIMER2_COMPARE1F or
T2IRQF.TIMER2_COMPARE2F is set to 1, depending of which compare value is reached. An interrupt
request is also generated if the corresponding interrupt mask in T2IRQM.TIMER2_COMPARE1M or
T2IRQM.TIMER2_COMPARE2M is set to 1.
22.1.6 Overflow Count
At each timer overflow, the 24-bit overflow counter is incremented by 1. The overflow counter value is read
through registers T2MOVF2:T2MOVF1:T2MOVF0 with register T2MSEL.T2MOVEFSEL set to 000. The
registers are latched as in the following description.
If one wants a unique timestamp, where both timer and overflow counter are latched at the same time, do
the following: Read T2M0 with T2MSEL.T2MSEL set to 000 and T2CTRL.LATCH_MODE set to 1. This
returns the low byte of the timer value, and also latches the high byte of the timer and the entire overflow
counter, so the rest of the timestamp is ready to be read.
208
Timer 2 (MAC Timer) SWRU191C–April 2009–Revised January 2012
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