Event Outputs (DMA Trigger and Radio Events)
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•
Long compare 1 (CC2541 only)
• Long compare 2 (CC2541 only)
The interrupt flags are given in the T2IRQF registers. The interrupt flag bits are set only by hardware and
can be cleared only by writing to the SFR register.
Each interrupt source can be masked by its corresponding mask bit in the T2IRQM register. An interrupt is
generated when the corresponding mask bit is set; otherwise, the interrupt is not generated. The interrupt
flag bit is set, however, regardless of the state of the interrupt mask bit.
22.3 Event Outputs (DMA Trigger and Radio Events)
Timer 2 has two event outputs, T2_EVENT1 and T2_EVENT2. These can be used as DMA triggers, as
inputs to the radio, for conditions in conditional instructions in the CSP on CC253x, for use by the BLE
stack on CC2540/41, or for timing TX or RX in CC2541 when running the radio in proprietary mode. The
event outputs can be configured individually to any of the following events:
• Timer overflow
• Timer compare 1
• Timer compare 2
• Overflow-count overflow
• Overflow-count compare 1
• Overflow-count compare 2
• Long compare 1 (CC2541 only)
• Long compare 2 (CC2541 only)
The DMA triggers are configured using T2EVTCFG.TIMER2_EVENT1_CFG and
T2EVTCFG.TIMER2_EVENT2_CFG.
22.4 Timer Start/Stop Synchronization
This section describes the synchronized timer start and stop.
22.4.1 General
The timer can be started and stopped synchronously with the 32-kHz clock rising edge. Note that this
event is derived from a 32-kHz clock signal, but is synchronous with the 32-MHz system clock and thus
has a period approximately equal to that of the 32-kHz clock period. Syncronous starting and stopping
must not be attempted unless both the 32-kHz clock and 32-MHz XOSC are running and stable.
At the time of a synchronous start, the timer is reloaded with new calculated values for the timer and
overflow count such that it appears that the timer has not been stopped.
22.4.2 Timer Synchronous Stop
After the timer has started running, i.e., entered timer RUN mode, it is stopped synchronously by writing 0
to T2CTRL.RUN when T2CTRL.SYNC is 1. After T2CTRL.RUN has been set to 0, the timer continues
running until the 32-kHz clock rising edge is sampled as 1. When this occurs, the timer is stopped, the
current Sleep Timer value is stored, and T2CTRL.STATE goes from 1 to 0.
22.4.3 Timer Synchronous Start
When the timer is in the IDLE mode, it is started synchronously by writing 1 to T2CTRL.RUN when
T2CTRL.SYNC is 1. After T2CTRL.RUN has been set to 1, the timer remains in the IDLE mode until the
32-kHz clock rising edge is detected. When this occurs, the timer first calculates new values for the 16-bit
timer value and for the 24-bit timer overflow count, based on the current and stored Sleep Timer values
210
Timer 2 (MAC Timer) SWRU191C–April 2009–Revised January 2012
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