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Memory
XREG Registers. The XREG registers are additional registers in the XDATA memory space. These
registers are mainly used for radio configuration and control. For more details regarding each register, see
the corresponding module/peripheral chapter. Table 2-2 gives a descriptive overview of the register
address space.
Table 2-2. Overview of XREG Registers
XDATA Address Register Name Description
Radio registers (see CC253x Radio Section 23.15 or CC2540
0x6000–0x61FF — Radio Section 24.1 or CC2541 Radio Section 25.12 for
complete list)
MONMUX Battery monitor MUX (CC2533)
0x61A6
OPAMPMC Operational amplifier mode control (CC2530/CC2531)
0x61AD OPAMPMC Operational amplifier mode control (CC2540)
0x6200–0x622B — USB registers (see Section 21.12 for complete list)
0x6230 I2CCFG I
2
C control
0x6231 I2CSTAT I
2
C status
0x6232 I2CDATA I
2
C data
0x6233 I2CADDR I
2
C own slave address
0x6234 I2CWC Wrapper control
0x6235 I2CIO GPIO
0x6243 OBSSEL0 Observation output control register 0
0x6244 OBSSEL1 Observation output control register 1
0x6245 OBSSEL2 Observation output control register 2
0x6246 OBSSEL3 Observation output control register 3
0x6247 OBSSEL4 Observation output control register 4
0x6248 OBSSEL5 Observation output control register 5
0x6249 CHVER Chip version
0x624A CHIPID Chip identification
0x624B TR0 Test register 0
0x6260 DBGDATA Debug interface write data
0x6262 SRCRC Sleep reset CRC
0x6264 BATTMON Battery monitor
0x6265 IVCTRL Analog control register
0x6270 FCTL Flash control
0x6271 FADDRL Flash address low
0x6272 FADDRH Flash address high
0x6273 FWDATA Flash write data
0x6276 CHIPINFO0 Chip information byte 0
0x6277 CHIPINFO1 Chip information byte 1
0x6281 IRCTL Timer 1 IR generation control
0x6290 CLD Clock-loss detection
Timer 1 channel 0 capture/compare control (additional XREG
0x62A0 T1CCTL0
mapping of SFR register)
Timer 1 channel 1 capture/compare control (additional XREG
0x62A1 T1CCTL1
mapping of SFR register)
Timer 1 channel 2 capture/compare control (additional XREG
0x62A2 T1CCTL2
mapping of SFR register)
0x62A3 T1CCTL3 Timer 1 channel 3 capture/compare control
0x62A4 T1CCTL4 Timer 1 channel 4 capture/compare control
Timer 1 channel 0 capture/compare value low (additional XREG
0x62A6 T1CC0L
mapping of SFR register)
Timer 1 channel 0 capture/compare value high (additional
0x62A7 T1CC0H
XREG mapping of SFR register)
35
SWRU191C–April 2009–Revised January 2012 8051 CPU
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