Timer 2 Registers
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T2CTRL (0x94) – Timer 2 Control Register
Bit Name Reset R/W Function
No.
7:4 – 0 R0 Reserved. Read as 0
3
LATCH_MODE
0 R/W 0:
Reading T2M0 with T2MSEL.T2MSEL = 000 latches the high byte of the timer,
making it ready to be read from T2M1. Reading T2MOVF0 with T2MSEL.T2MOVFSEL
= 000 latches the two most-significant bytes of the overflow counter, making it
possible to read these from T2MOVF1 and T2MOVF2.
1:
Reading T2M0 with T2MSEL.T2MSEL = 000 latches the high byte of the timer and
the entire overflow counter at once, making it possible to read the values from T2M1,
T2MOVF0, T2MOVF1, and T2MOVF2.
2
STATE
0 R State of Timer 2
0: Timer idle
1: Timer running
1
SYNC
1 R/W 0: Starting and stopping of timer is immediate, i.e., synchronous with clk_rf_32m.
1: Starting and stopping of timer happens at the first positive edge of the 32-kHz clock.
Read Section 22.4 for more details regarding timer start and stop.
0
RUN
0 R/W Write 1 to start timer, write 0 to stop timer. When read, it returns the last written
value.
T2EVTCFG (0x9C) – Timer 2 Event Configuration (CC253x/CC2540)
Bit Name Reset R/W Function
No.
7 – 0 R0 Reserved. Read as 0
6:4
TIMER2_EVENT2_CFG
0 R/W Selects the event that triggers a T2_EVENT2 pulse
000: t2_per_event
001: t2_cmp1_event
010: t2_cmp2_event
011: t2ovf_per_event
100: t2ovf_cmp1_event
101: t2ovf_cmp2_event
110: Reserved
111: No event
3 – 0 R0 Reserved. Read as 0
2:0
TIMER2_EVENT1_CFG
0 R/W Selects the event that triggers a T2_EVENT1 pulse
000: t2_per_event
001: t2_cmp1_event
010: t2_cmp2_event
011: t2ovf_per_event
100: t2ovf_cmp1_event
101: t2ovf_cmp2_event
110: Reserved
111: No event
216
Timer 2 (MAC Timer) SWRU191C–April 2009–Revised January 2012
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