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Interrupts
If one wants to read just the overflow counter without reading timer first, read T2MOVF0 with
T2MSEL.T2MOVFSEL set to 000 and T2CTRL.LATCH_MODE set to 0. This returns the low byte of the
overflow counter, and latches the two most-significant bytes of the overflow counter so the values are
ready to be read.
22.1.7 Overflow-Count Update
The overflow count value can be updated by writing to registers T2MOVF2:T2MOVF1:T2MOVF0 with
T2MSEL.T2MOVFSEL set to 000. Always write the least-significant byte first, and always write all three
bytes. The write takes effect once the high byte is written.
22.1.8 Overflow-Count Overflow
At the same time as the overflow counter counts to a value that is equal to the overflow period setting, an
overflow period event occurs. When the period event occurs, the overflow counter is set to 0x00 0000. If
the overflow interrupt mask bit T2IRQM.TIMER2_OVF_PERM is 1, an interrupt request is generated. The
interrupt flag bit T2IRQF.TIMER2_OVF_PERF is set to 1, regardless of the interrupt mask value.
22.1.9 Overflow-Count Compare
Two compare values may be set for the overflow counter. The compare values are set by writing to
T2MOVF2:T2MOVF1:T2MOVF0 with register T2MSEL.T2MOVFSEL set to 011 or 100. At the same time as
the overflow counter counts to a value equal to one of the overflow count compare values, an overflow
count compare event occurs. If the corresponding overflow compare interrupt mask bit
T2IRQM.TIMER2_OVF_COMPARE1M or T2IRQM.TIMER2_OVF_COMPARE2M is 1, an interrupt request is
generated. The interrupt flags bit T2IRQF.TIMER2_OVF_COMPARE1F and
T2IRQF.TIMER2_OVF_COMPARE2F are set to 1, regardless of the interrupt mask value.
22.1.10 Capture Input
Timer 2 has a timer capture function, which captures the time when the start-of-frame delimiter (SFD)
status in the radio goes high.
When the capture event occurs, the current timer value is captured in the capture register. The capture
value can be read from registers T2M1:T2M0 if register T2MSEL.T2MSEL is set to 001. The value of the
overflow count is also captured at the time of the capture event and can be read from registers
T2MOVF2:T2MOVF1:T2MOVF0 if T2MSEL.T2MOVFSEL is set to 001.
22.1.11 Long Compare (CC2541 Only)
In the CC2541, two compare values may be set for the combination of the 16-bit timer and the overflow
counter. The compare values are a combination of either timer compare 1 and overflow compare 1, or
timer compare 2 and overflow compare 2. These combinations are known as the long compare 1 and long
compare 2 values, respectively. At the same time as the combination of the 16-bit timer and the 24-bit
overflow counter counts to a value equal to one of the long compare values, a long compare event occurs.
If the corresponding overflow compare interrupt mask bit T2IRQM.TIMER2_LONG_COMPARE1M or
T2IRQM.TIMER2_LONG_COMPARE2M is 1, an interrupt request is generated. The corresponding interrupt
flag bit T2IRQF.TIMER2_LONG_COMPARE1F or T2IRQF.TIMER2_LONG_COMPARE2F is set to 1,
regardless of the interrupt mask value.
22.2 Interrupts
The timer has six (eight on CC2541) individually maskable interrupt sources. These are the following:
• Timer overflow
• Timer compare 1
• Timer compare 2
• Overflow-count overflow
• Overflow-count compare 1
• Overflow-count compare 2
209
SWRU191C–April 2009–Revised January 2012 Timer 2 (MAC Timer)
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