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ADC Operation
The single-ended inputs AIN0 through AIN7 are represented by channel numbers 0 to 7. Channel
numbers 8 through 11 represent the differential inputs consisting of AIN0–AIN1, AIN2–AIN3, AIN4–AIN5,
and AIN6–AIN7. Channel numbers 12 through 15 represent GND (12), temperature sensor (14), and
AVDD5/3 (15), with channel 13 being reserved. These values are used in the ADCCON2.SCH and
ADCCON3.SCH fields.
The ADC input is a switched capacitance stage which draws current during the conversion. As an
example, the equivalent input impedance of a typical device was found to be 176 kΩ when used with an
input voltage of 3 V, a 512× decimation rate, and the internal reference.
12.2.2 ADC Conversion Sequences
The ADC can perform a sequence of conversions and move the results to memory (through DMA) without
any interaction from the CPU.
The conversion sequence can be influenced with the APCFG register (see Section 7.6.6), in that the eight
analog inputs to the ADC come from I/O pins that are not necessarily programmed to be analog inputs. If
a channel should normally be part of a sequence, but the corresponding analog input is disabled in the
APCFG register, then that channel is skipped. When using differential inputs, both pins in a differential pair
must set as analog input pins in the APCFG register.
The ADCCON2.SCH register bits are used to define an ADC conversion sequence from the ADC inputs. If
ADCCON2.SCH is set to a value less than 8, the conversion sequence contains a conversion from each
channel from 0 up to and including the channel number programmed in ADCCON2.SCH. When
ADCCON2.SCH is set to a value between 8 and 12, the sequence consists of differential inputs, starting at
channel 8 and ending at the programmed channel. For ADCCON2.SCH greater than or equal to 12, the
sequence consists of the selected channel only.
12.2.3 Single ADC Conversion
In addition to this sequence of conversions, the ADC can be programmed to perform a single conversion
from any channel. Such a conversion is triggered by writing to the ADCCON3 register. The conversion
starts immediately unless a conversion sequence is already ongoing, in which case the single conversion
is performed as soon as that sequence is finished.
12.2.4 ADC Operating Modes
This section describes the operating modes and initialization of conversions.
The ADC has three control registers: ADCCON1, ADCCON2, and ADCCON3. These registers are used to
configure the ADC and to report status.
The ADCCON1.EOC bit is a status bit that is set high when a conversion ends and cleared when ADCH is
read.
The ADCCON1.ST bit is used to start a sequence of conversions. A sequence starts when this bit is set
high, ADCCON1.STSEL is 11, and no conversion is currently running. When the sequence is completed,
this bit is automatically cleared.
The ADCCON1.STSEL bits select the event that starts a new sequence of conversions. The options which
can be selected are rising edge on external pin P2.0, end of previous sequence, a Timer 1 channel 0
compare event, or ADCCON1.ST is 1.
The ADCCON2 register controls how the sequence of conversions is performed.
ADCCON2.SREF is used to select the reference voltage. The reference voltage should only be changed
when no conversion is running.
The ADCCON2.SDIV bits select the decimation rate, thereby also the resolution and time required to
complete a conversion, and hence the sample rate. The decimation rate should only be changed when no
conversion is running.
The last channel of a sequence is selected with the ADCCON2.SCH bits as described previoiusly.
139
SWRU191C–April 2009–Revised January 2012 ADC
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