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Registers
RFTXFRD (0x61D3) – Tx FIFO Read Register
Bit
Name Reset R/W Description
No.
7:0
D
0x00 R
When this register is read, the data in Tx FIFO address offset RFTXFRP
from the start of the Tx FIFO area is returned (see Figure 25-1).
RFTXFRP (and RFTXFSRP if RFFCFG.TXAUTOCOMMIT = 1) is
incremented by 1 modulo 0x80 unless the read fails.
RFTXFWP (0x61D4) – Tx FIFO Write Pointer
Bit
Name Reset R/W Description
No.
7 – 0 R Reserved
6:0
D
000 R/W Tx FIFO write pointer. This is the offset into Tx FIFO the next write
0000 operation writes to.
RFTXFRP (0x61D5) – Tx FIFO Read Pointer
Bit
Name Reset R/W Description
No.
7 – 0 R Reserved
6:0
D
000 R/W Tx FIFO read pointer. This is the offset into Tx FIFO the next read
0000 operation reads from.
RFTXFSWP (0x61D6) – Tx FIFO Start-of-Frame Write Pointer
Bit
Name Reset R/W Description
No.
7 – 0 R Reserved
6:0
D
000 R/W Tx FIFO start of written package. This is the point to which the write
0000 pointer can be reset if a discard command is issued.
RFTXFSRP (0x61D7) – Tx FIFO Start-of-Frame Read Pointer
Bit
Name Reset R/W Description
No.
7 – 0 R Reserved
6:0
D
0x00 R/W Tx FIFO start-of-read package. This is the start of the allocated part of the
Tx FIFO.
BSP_P0 (0x61E0) – CRC Polynomial Byte 0
Bit
Name Reset R/W Description
No.
7:0
P[7:0]
0x00 R/W Bits 7:0 of p register in CRC sub-module
BSP_P1 (0x61E1) – CRC Polynomial Byte 1
Bit
Name Reset R/W Description
No.
7:0
P[15:8]
0x5B R/W Bits 15:8 of p register in CRC sub-module
BSP_P2 (0x61E2) – CRC Polynomial Byte 2
Bit
Name Reset R/W Description
No.
7:0
P[23:16]
0x06 R/W Bits 23:16 of p register in CRC sub-module
BSP_P3 (0x61E3) – CRC Polynomial Byte 3
Bit
Name Reset R/W Description
No.
7:0
P[31:24]
0x00 R/W Bits 31:24 of p register in CRC sub-module
351
SWRU191C–April 2009–Revised January 2012 CC2541 Proprietary Mode Radio
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