RESET
WATCHDOG
TIMER
IRQ CTRL
CC2530/CC2531
FLASH CTRL
DEBUG
INTERFACE
CLOCK MUX
and
CALIBRATION
DMA
8051 CPU
CORE
32-MHz
CRYSTAL OSC
32.768-kHz
CRYSTAL OSC
HIGH-
SPEED
RC-OSC
USART 0
USART 1
TIMER 1 (16-Bit)
TIMER 3 (8-Bit)
TIMER 4 (8-Bit)
TIMER 2
(IEEE 802.15.4 MAC TIMER)
32/64/128/256-KB
FLASH
8-KB SRAM
RESET_N
XOSC_Q2
XOSC_Q1
P2_4
P1_7
P0_7
P2_3
P1_6
P0_6
P2_2
P1_5
P0_5
P1_2
P0_2
P2_1
P1_4
P0_4
P1_1
P0_1
P2_0
P1_3
P0_3
P1_0
P0_0
MODULATOR
DEMODULATOR
AND AGC
RECEIVE TRANSMIT
FREQUENCY
SYNTHESIZER
SYNTH
RF_P RF_N
B0301-03
RADIO DATA INTERFACE
CSMA/CA STROBE PROCESSOR
RADIO REGISTERS
FIFO and FRAME CONTROL
SFR Bus
SFR Bus
12-BIT -
ADC
D S
AES
ENCRYPTION
AND
DECRYPTION
MEMORY
ARBITER
SFR
IRAM
XRAM
PDATA
32-kHz
RC-OSC
I/O CONTROLLER
DIGITAL
ANALOG
MIXED
POWER MANAGEMENT CONTROLLER
ON-CHIP VOLTAGE
REGULATOR
POWER-ON RESET
BROWNOUT
VDD (2 V–3.6 V)
DCOUPL
SLEEP TIMER
BATTERY MONITOR (CC2533 ONLY)
USB
USB
PHY
1-KB
FIFO SRAM
DP
DM
CC2531
OP-AMP
ANALOG COMPARATOR
Overview
www.ti.com
1.1 Overview
The block diagrams in Figure 1-1 and Figure 1-2 show the different building blocks of the CC253x and
CC2540/41 device family. Not all features and functions of all modules or peripherals are present on all
devices of the CC253x/CC2540/41; hence, see the device-specific data sheet for a device-specific block
diagram.
Figure 1-1. CC253x Block Diagram
20
Introduction SWRU191C–April 2009–Revised January 2012
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