24
T OH
ST(max)
ck
(2 1) P T
t
K
- ´ +
£
Timer 2 Registers
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Calculation of New Timer Value and Overflow Count Value
N
c
= Current Sleep Timer value
N
ST
= Stored Sleep Timer value
K
ck
= Clock ratio = 976.5625
(1)
stw = Sleep Timer width = 24
P
T
= Timer 2 period
P
OVF
= Overflow period
O
ST
= Stored overflow-count value
O
TICK
= Overflow tics while sleeping
t
ST
= Stored timer value
T
OH
= Overhead = 86
N
t
= N
c
– N
ST
N
t
≤ 0 → N
d
= 2
stw
+ N
t
; N
t
> 0 → N
d
= N
t
C = N
d
× K
ck
+ T
ST
+ T
OH
(rounded to nearest integer value)
T = C mod P
T
Timer2Value = T
O = (O
TICK
+ O
ST
) mod P
OVF
Timer2OverflowCount = O
(1)
Clock ratio of Timer 2 clock frequency (32 MHz) and Sleep Timer clock frequency (32 kHz)
For a given Timer 2 period value, P
T
, there is a maximum duration between Timer 2 synchronous stop and
start for which the timer value is correctly updated after starting. The maximum value is given in terms of
the number of Sleep Timer clock periods, i.e., 32-kHz clock periods, t
ST(max)
.
22.5 Timer 2 Registers
The SFR registers associated with Timer 2 are listed in this section. These registers are the following:
•
T2MSEL
– Timer 2 multiplexed register control
•
T2M1
– Timer 2 multiplexed count high
•
T2M0
– Timer 2 multiplexed count low
•
T2MOVF2
– Timer 2 multiplexed overflow count 2
•
T2MOVF1
– Timer 2 multiplexed overflow count 1
•
T2MOVF0
– Timer 2 multiplexed overflow count 0
•
T2IRQF
– Timer 2 interrupt flags
•
T2IRQM
– Timer 2 interrupt masks
•
T2EVTCFG
– Timer 2 event output configuration
•
T2CTRL
– Timer 2 configuration
Timer 2 has several multiplexed registers. This is to be able to fit all the registers into the limited SFR
address space. The internal registers listed in Table 22-1 can be accessed indirectly through T2M0, T2M1,
T2MOVF0, T2MOVF1, and T2MOVF2.
212
Timer 2 (MAC Timer) SWRU191C–April 2009–Revised January 2012
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