Registers
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FSMSTAT1 (0x6193) – Radio Status Register
Bit Name Reset R/W Description
No.
7
FIFO
0 R FIFO is high whenever there is data in the RXFIFO. Low during RXFIFO overflow
6
FIFOP
0 R
FIFOP is set high when there are more than FIFOP_THR bytes of data in the
RXFIFO that have passed frame filtering.
FIFOP is set high when there is at least one complete frame in the RXFIFO.
FIFOP is set low again when a byte is read from the RXFIFO and this leaves
FIFOP_THR bytes in the FIFO.
FIFOP is high during RXFIFO overflow.
5
SFD
0 R In TX
0: When a complete frame with SFD has been sent or no SFD has been sent
1: SFD has been sent.
In RX
0: When a complete frame has been received or no SFD has been received
1: SFD has been received.
4
CCA
0 R
Clear-channel assessment. Dependent on CCA_MODE settings. Seethe following
description of CCACTRL1.
3
SAMPLED_CCA
0 R Contains a sampled value of the CCA. The value is updated whenever a
SSAMPLECCA or STXONCCA strobe is issued.
2
LOCK_STATUS
0 R 1 when PLL is in lock, otherwise 0.
1
TX_ACTIVE
0 R Status signal, active when FFCTRL is in one of the transmit states
0
RX_ACTIVE
0 R Status signal, active when FFCTRL is in one of the receive states
FIFOPCTRL (0x6194) – FIFOP Threshold
Bit Name Reset R/W Description
No.
7 – 0 R0 Read as zero
6:0
FIFOP_THR[6:0]
100 0000 R/W
Threshold used when generating FIFOP signal
FSMCTRL (0x6195) – FSM Options
Bit Name Reset R/W Description
No.
7:2 – 0000 00 R0 Read as zero
1
SLOTTED_ACK
0 R/W Controls timing of transmission of acknowledge frames
0: The acknowledge frame is sent 12 symbol periods after the end
of the received frame which requests the aknowledge.
1: The acknowledge frame is sent at the first backoff-slot boundary
more than 12 symbol periods after the end of the received frame
which requests the aknowledge.
0
RX2RX_TIME_OFF
1 R/W Defines whether or not a 12-symbol time-out should be used after frame
reception has ended.
0: No time-out
1: 12-symbol-period time-out
274
CC253x Radio SWRU191C–April 2009–Revised January 2012
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