Parameters and firmware blocks
228
(3) ENC1 DI2 _– Encoder 1 position Rising edge of DI2
(4) ENC1 DI2 –_ Encoder 1 position Falling edge of DI2
(5) Reserved.
(6) ENC1 Zerop Encoder 1 position Zero pulse
(7) ENC1 DI1_– z Encoder 1 position First zero pulse after rising edge
of DI1
(8) ENC1 DI1–_ z Encoder 1 position First zero pulse after falling edge
of DI1
(9) ENC1 DI1=1 z Encoder 1 position First zero pulse when DI1 = 1
(10) ENC1 DI1=0 z Encoder 1 position First zero pulse when DI1 = 0
(11) ENC1 DI2_– z Encoder 1 position First zero pulse after rising edge
of DI2
(12) ENC1 DI2–_ z Encoder 1 position First zero pulse after falling edge
of DI2
(13) ENC1 DI2=1 z Encoder 1 position First rising edge of zero pulse
when DI2 = 1
(14) ENC1 DI2=0 z Encoder 1 position First rising edge of zero pulse
when DI2 = 0
(15) ENC2 DI1 _– Encoder 2 position Rising edge of DI1
(16) ENC2 DI1 –_ Encoder 2 position Falling edge of DI1
(17) ENC2 DI2 _– Encoder 2 position Rising edge of DI2
(18) ENC2 DI2 –_ Encoder 2 position Falling edge of DI2
(19) Reserved.
(20) ENC2 Zerop Encoder 2 position Zero pulse
(21) ENC2 DI1_– z Encoder 2 position First zero pulse after rising edge
DI1
(22) ENC2 DI1–_ z Encoder 2 position First zero pulse after falling edge
of DI1
(23) ENC2 DI1=1 z Encoder 2 position First zero pulse when DI1 = 1
(24) ENC2 DI1=0 z Encoder 2 position First zero pulse when DI1 = 0
(25) ENC2 DI2_– z Encoder 2 position First zero pulse after rising edge
of DI2
(26) ENC2 DI2–_ z Encoder 2 position First zero pulse after falling edge
of DI2
(27) ENC2 DI2=1 z Encoder 2 position First zero pulse when DI2 = 1