AT&T PC 6300 - Test Descriptions

DIAGNOSTICS
Test Descriptions
The following sequence is executed when the power switch is
turned ON or when the hardware RESET button is pressed.
1. The system reset vector at FFFFO executes an unconditional
direct intersegment jump instruction to the 8086 CPU test.
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2. The 8086 CPU test is performed. Interrupts are disabled.
First, the CPU's status flags are tested using the
accumulator and the processor control and conditional j |
control transfer instruction classes. Second, the CPU's 1J
general and segment registers are tested with a test pattern.
Third, a typical instruction from each of the CPU's data
transfer, arithmetic, logical, and string manipulation
instruction classes are tested. Fourth, a set of the CPU's
addressing modes are tested on ROM. Fifth, the stack _
segment and pointer registers are initialized to address the ,1
ROM stack, and the call/return instructions are tested.
Testing the CPU's software-interrupt instruction capability ^
is postponed until after the ROM and RAM modules have H
been tested. The CPU's hardware-interrupt diagnostics are _J
postponed until after the 8253 real-time clock channel, the
8041 Keyboard peripheral interface, and the 8259 interrupt
controller have been initialized and tested, because all three
are involved in the testing.
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3. The Keyboard peripheral interface chip (8041 or 8741) is
programmed and initialized, the lights go off, and a beep is
heard.
4-10
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